From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 365DFC531DC for ; Tue, 20 Aug 2024 17:08:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=aQyEuqNnkwz3WhAvQ9OyOp/Y67j7xpvJJsdkhU7zjKs=; b=FV6crf8GzufIi4NmQisOqnWbC1 UM8bv4/jFxUoQTIO5ou+/+PN/Rv4F34XffdXTbCH1NAhhoGTCvJ+vpwM3qliX3+u4NVPLHas6h8qB eVd0kIb/VSGweu6aVnYMsc33cxmzosOergyKpQTKKEXcOkPDxC07prKlhiF5WNGcHoQj7MdVNlXsI l+/1VMJ7gI+NcgmntK5+hGr+DMG9zWQLif5l09NjTEB0Zouy7eQ2t4G24gHtldGDkA2T/cU+VAmNt riDcgrC72MWiD2dNbB6qBJI7FoRyPu3iL22rWjDnYqB3UBp+5UGBem/vvHqBFA8VI2/y83RSLg3Fi 61DwKCZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sgSLJ-000000067EN-0dx5; Tue, 20 Aug 2024 17:08:25 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sgSKb-00000006763-0GHE; Tue, 20 Aug 2024 17:07:42 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id E1875CE0AE7; Tue, 20 Aug 2024 17:07:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6B55C4AF13; Tue, 20 Aug 2024 17:07:31 +0000 (UTC) Date: Tue, 20 Aug 2024 18:07:29 +0100 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy , Kees Cook , "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , Thiago Jung Bauermann , Ross Burton , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v10 19/40] arm64/gcs: Context switch GCS state for EL0 Message-ID: References: <20240801-arm64-gcs-v10-0-699e2bd2190b@kernel.org> <20240801-arm64-gcs-v10-19-699e2bd2190b@kernel.org> <0f6fd3ec-2481-4507-af0e-3cbbb7406b54@sirena.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0f6fd3ec-2481-4507-af0e-3cbbb7406b54@sirena.org.uk> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240820_100741_471383_37A56E12 X-CRM114-Status: GOOD ( 29.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 19, 2024 at 04:44:42PM +0100, Mark Brown wrote: > On Mon, Aug 19, 2024 at 12:46:13PM +0100, Catalin Marinas wrote: > > On Thu, Aug 01, 2024 at 01:06:46PM +0100, Mark Brown wrote: > > > + /* > > > + * Ensure that GCS changes are observable by/from other PEs in > > > + * case of migration. > > > + */ > > > + if (task_gcs_el0_enabled(current) || task_gcs_el0_enabled(next)) > > > + gcsb_dsync(); [...] > > What's the GCSB DSYNC supposed to do here? The Arm ARM talks about > > ordering between GCS memory effects and other memory effects. I haven't > > looked at the memory model in detail yet (D11.9.1) but AFAICT it has > > nothing to do with the system registers. We'll need this barrier when > > ordering is needed between explicit or implicit (e.g. BL) GCS accesses > > and the explicit classic memory accesses. Paging comes to mind, so maybe > > flush_dcache_page() would need this barrier. ptrace() is another case if > > the memory accessed is a GCS page. I can see you added it in other > > places, I'll have a look as I go through the rest. But I don't think one > > is needed here. > > It's not particuarly for the system registers, is there's so that > anything else that looks at the task's GCS sees the current state. Ah, so that's the to ensure that any writes on the CPU to the GCS stack would be observable if the task appears on a different CPU (together with the additional classic ordering/spinlocks used for the run queues). Maybe update the comment to say "GCS memory effects" instead of "GCS changes". I read the latter as GCS sysreg changes. Something like below would make it clearer: /* * Ensure that GCS memory effects of the 'prev' thread are * ordered before other memory accesses with release semantics * (or preceded by a DMB) on the current PE. In addition, any * memory accesses with acquire semantics (or succeeded by a * DMB) are ordered before GCS memory effects of the 'next' * thread. This will ensure that the GCS memory effects are * visible to other PEs in case of migration. */ Feel free to rephrase as you see fit. > I'm pretty confident this excessive, the goal was to err on the side > of correctness and then relax later. I think we are missing some. Paging should be ok as we have a pte change and TLBI and IIRC the same rules as for standard memory accesses apply. ptrace() memory accesses may need something though I'm fine with considering this a best effort (we can't guarantee anyway if any accesses are on different CPUs). I haven't got to the signal handling patch yet. -- Catalin