From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0819C5320E for ; Thu, 22 Aug 2024 09:52:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XuEhyhlXkCFAcR7Oanix4dVftstAX9q47SpS0TB4ZHs=; b=UkBdnhfCT7C0fg6mxB2/KtOUyw 50OMCjEe3dy147H6FBIx/KIAL4e0fpQzijlSQmidbzgKkI0oz7zw2r1kYBul/cDXY7PRpUQF6t17S 6s7jpbHDiCqP9IcRenRc0itmwli5sC16+SVdpjxvfb/U9bMwsg2OKgKg2jepm3+NTT1N8HLy6OoM3 r2eS7/eQiQC7drWAfLw5H+SNUW29sYXaOaaeMDNAMKSE/VN6oLl2P6fD6DAqG4yt0m+TMiyyzCg3g K6eoIzeAW/yNlDDsbQzz/p8nPzhUnNCcapLrRjb12W808A8kn4hI34+ZJ62Hr3YJc/XZGJk2DU0rz Rr6+KimQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4UV-0000000CKy6-2CJY; Thu, 22 Aug 2024 09:52:27 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4Su-0000000CKUZ-3Tf8 for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 09:50:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B065DA7; Thu, 22 Aug 2024 02:51:14 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 566383F66E; Thu, 22 Aug 2024 02:50:47 -0700 (PDT) Date: Thu, 22 Aug 2024 10:50:44 +0100 From: Mark Rutland To: Andre Przywara Cc: linux-arm-kernel@lists.infradead.org, akos.denke@arm.com, luca.fancellu@arm.com, maz@kernel.org Subject: Re: [BOOT-WRAPPER v2 07/10] Unify assembly setup paths Message-ID: References: <20240812101555.3558589-1-mark.rutland@arm.com> <20240812101555.3558589-8-mark.rutland@arm.com> <20240821175445.27e6fa9d@donnerap.manchester.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240821175445.27e6fa9d@donnerap.manchester.arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_025049_179814_EEE111FF X-CRM114-Status: GOOD ( 32.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 21, 2024 at 05:54:45PM +0100, Andre Przywara wrote: > On Mon, 12 Aug 2024 11:15:52 +0100 > Mark Rutland wrote: > > > The early assembly paths for EL3/Secure-PL1 and EL2/Hyp are almost > > identical aside from the EL3/Secure-PL1 paths calling gic_secure_init(). > > > > Simplify the easlery assembly paths by conditionally calling Whoops; I'll s/easlery/early/ here. > > gic_secure_init() from cpu_init_arch(), allowing the EL3/Secure-PL1 and > > EL2/Hyp paths to be unified. > > > > In order to call gic_secure_init() from C code we need to expose a > > prototype for gic_secure_init(), requiring a new header. For > > clarity the existing headers are renamed to > > and are included through the common header. > > > > Signed-off-by: Mark Rutland > > Acked-by: Marc Zyngier > > Cc: Akos Denke > > Cc: Andre Przywara > > Cc: Luca Fancellu > > Thanks, that seems like a nice cleanup and refactoring, and looks good to > me: > > Reviewed-by: Andre Przywara Cheers! > Just not sure what to do about the TODO comments in there? They're a note that the AArch32 code doesn't currently initialize registers which are UNKNOWN at reset, and without the notes it looks a little odd to have those labels at all ratehr than branching directly to reset_common() above. I'd prefer to keep those for now to indicate that there are known issues here. Mark. > > Cheers, > Andre > > > --- > > arch/aarch32/boot.S | 20 ++++++-------------- > > arch/aarch32/include/asm/{gic-v3.h => gic.h} | 2 +- > > arch/aarch32/init.c | 5 ++++- > > arch/aarch64/boot.S | 17 ++++------------- > > arch/aarch64/include/asm/{gic-v3.h => gic.h} | 2 +- > > arch/aarch64/init.c | 5 ++++- > > common/gic-v3.c | 2 +- > > common/gic.c | 2 +- > > include/gic.h | 16 ++++++++++++++++ > > 9 files changed, 38 insertions(+), 33 deletions(-) > > rename arch/aarch32/include/asm/{gic-v3.h => gic.h} (91%) > > rename arch/aarch64/include/asm/{gic-v3.h => gic.h} (92%) > > create mode 100644 include/gic.h > > > > diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S > > index 78d19a0..8b6ffac 100644 > > --- a/arch/aarch32/boot.S > > +++ b/arch/aarch32/boot.S > > @@ -53,22 +53,14 @@ reset_at_svc: > > movs pc, lr > > > > reset_at_mon: > > - cpuid r0, r1 > > - bl find_logical_id > > - cmp r0, #MPIDR_INVALID > > - beq err_invalid_id > > - > > - bl setup_stack > > - > > - bl cpu_init_bootwrapper > > - > > - bl cpu_init_arch > > - > > - bl gic_secure_init > > - > > - b start_bootmethod > > + // TODO initialise monitor state > > + b reset_common > > > > reset_at_hyp: > > + // TODO initialise hyp state > > + b reset_common > > + > > +reset_common: > > cpuid r0, r1 > > bl find_logical_id > > cmp r0, #MPIDR_INVALID > > diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic.h > > similarity index 91% > > rename from arch/aarch32/include/asm/gic-v3.h > > rename to arch/aarch32/include/asm/gic.h > > index b28136a..0b9425d 100644 > > --- a/arch/aarch32/include/asm/gic-v3.h > > +++ b/arch/aarch32/include/asm/gic.h > > @@ -1,5 +1,5 @@ > > /* > > - * arch/aarch32/include/asm/gic-v3.h > > + * arch/aarch32/include/asm/gic.h > > * > > * Copyright (C) 2015 ARM Limited. All rights reserved. > > * > > diff --git a/arch/aarch32/init.c b/arch/aarch32/init.c > > index 35da37c..cb67bf6 100644 > > --- a/arch/aarch32/init.c > > +++ b/arch/aarch32/init.c > > @@ -7,6 +7,7 @@ > > * found in the LICENSE.txt file. > > */ > > #include > > +#include > > #include > > #include > > > > @@ -56,8 +57,10 @@ bool cpu_init_psci_arch(void) > > > > void cpu_init_arch(void) > > { > > - if (read_cpsr_mode() == PSR_MON) > > + if (read_cpsr_mode() == PSR_MON) { > > cpu_init_monitor(); > > + gic_secure_init(); > > + } > > > > mcr(CNTFRQ, COUNTER_FREQ); > > } > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > > index 0ac0c98..98ae77d 100644 > > --- a/arch/aarch64/boot.S > > +++ b/arch/aarch64/boot.S > > @@ -43,19 +43,7 @@ reset_at_el3: > > msr sctlr_el3, x0 > > isb > > > > - cpuid x0, x1 > > - bl find_logical_id > > - cmp x0, #MPIDR_INVALID > > - b.eq err_invalid_id > > - bl setup_stack > > - > > - bl cpu_init_bootwrapper > > - > > - bl cpu_init_arch > > - > > - bl gic_secure_init > > - > > - b start_bootmethod > > + b reset_common > > > > /* > > * EL2 initialization > > @@ -70,6 +58,9 @@ reset_at_el2: > > msr sctlr_el2, x0 > > isb > > > > + b reset_common > > + > > +reset_common: > > cpuid x0, x1 > > bl find_logical_id > > cmp x0, #MPIDR_INVALID > > diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic.h > > similarity index 92% > > rename from arch/aarch64/include/asm/gic-v3.h > > rename to arch/aarch64/include/asm/gic.h > > index 2447480..9d716f6 100644 > > --- a/arch/aarch64/include/asm/gic-v3.h > > +++ b/arch/aarch64/include/asm/gic.h > > @@ -1,5 +1,5 @@ > > /* > > - * arch/aarch64/include/asm/gic-v3.h > > + * arch/aarch64/include/asm/gic.h > > * > > * Copyright (C) 2015 ARM Limited. All rights reserved. > > * > > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > > index 49abdf7..68c220b 100644 > > --- a/arch/aarch64/init.c > > +++ b/arch/aarch64/init.c > > @@ -7,6 +7,7 @@ > > * found in the LICENSE.txt file. > > */ > > #include > > +#include > > #include > > #include > > > > @@ -172,8 +173,10 @@ bool cpu_init_psci_arch(void) > > > > void cpu_init_arch(void) > > { > > - if (mrs(CurrentEL) == CURRENTEL_EL3) > > + if (mrs(CurrentEL) == CURRENTEL_EL3) { > > cpu_init_el3(); > > + gic_secure_init(); > > + } > > > > msr(CNTFRQ_EL0, COUNTER_FREQ); > > } > > diff --git a/common/gic-v3.c b/common/gic-v3.c > > index 6207007..4d8e620 100644 > > --- a/common/gic-v3.c > > +++ b/common/gic-v3.c > > @@ -10,7 +10,7 @@ > > #include > > > > #include > > -#include > > +#include > > #include > > > > #define GICD_CTLR 0x0 > > diff --git a/common/gic.c b/common/gic.c > > index 04d4289..15a3410 100644 > > --- a/common/gic.c > > +++ b/common/gic.c > > @@ -10,7 +10,7 @@ > > #include > > > > #include > > -#include > > +#include > > #include > > > > #define GICD_CTLR 0x0 > > diff --git a/include/gic.h b/include/gic.h > > new file mode 100644 > > index 0000000..127f82b > > --- /dev/null > > +++ b/include/gic.h > > @@ -0,0 +1,16 @@ > > +/* > > + * include/gic.h > > + * > > + * Copyright (C) 2024 ARM Limited. All rights reserved. > > + * > > + * Use of this source code is governed by a BSD-style license that can be > > + * found in the LICENSE.txt file. > > + */ > > +#ifndef __GIC_H > > +#define __GIC_H > > + > > +#include > > + > > +void gic_secure_init(void); > > + > > +#endif >