From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46FA8CD13CF for ; Mon, 2 Sep 2024 09:32:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To: Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VJE54eIljBo+04QQocBk6CxFcwFwa7n+6hpWhqzR/Xc=; b=MpWkN7Z1rLX6sTqkXN5b5ezBT1 IYqu/hFBA64OWkz48rIbv7WiRpyizw4cg9x0+Q+qhMT8Ndz+dEsISIzvQshYiiIPXv9Lb6Zyv/sWT ROmlpIgX2dxFK6HgHQCOhqZ7hKRrs/nz3OWtc6hzin5AWffpLXlJdSptcen7K4Kiih03wkYe7eZAw LoUCYiFZj/70mf/RdhFr1OKpR2O2Kbk8KXummNylSlVrqRy6wUp2lELIwvJNqMt+pnyW/o7Cdic/W U4Q7NbGNRI/JswQppf2OeydfNYfoE5Z8fw2a5e6cQjXNcrXmmzsD4MyAJ2Sh8AL8duN3KohQ7AC+9 kno5A2lg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sl3Po-0000000DiFk-1h0p; Mon, 02 Sep 2024 09:32:04 +0000 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sl3Nn-0000000DhrV-47yy for linux-arm-kernel@lists.infradead.org; Mon, 02 Sep 2024 09:30:01 +0000 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5c247dd0899so9295a12.1 for ; Mon, 02 Sep 2024 02:29:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1725269398; x=1725874198; darn=lists.infradead.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=VJE54eIljBo+04QQocBk6CxFcwFwa7n+6hpWhqzR/Xc=; b=PCXpN2Ly93GKSP/qFkiCkdQvVnwJB1ODKueUb5d1ftsZGRY7OL8xjWEEF5bbdXmLWZ 9vde88SQCyfBetHb56QLTjzzNyyCynIcxSWWCSBbKTct7x3lgnbsU1AmtFAHA6c2wrje Ujsy/bXyKofMECJgQoA709ysFSn5kBBgFaBgMY+p3Lhq1I12N3Tj0O78zNNOaG+oYj0G OWdlXDBAGWd1HLdrJjkU9KQj0NuTTe3Gs7YPNSVTHGLU1dPKYWjyWrLrRQztz6/YmtFO 4ubb0DMYBWzqay/ZQ+QSmyXurBdSr8D8EFNxnQY3idzwwVf+bhVbC/1n0lXlIbQkSWNP Ml2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725269398; x=1725874198; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VJE54eIljBo+04QQocBk6CxFcwFwa7n+6hpWhqzR/Xc=; b=cQ2MwXAmgO5Pt8bUhgsPbih4wtPbhcnM8jG5t1XXdYMjbddAInwGINLU4YGRVPL1Cq A1cRiUqRUA9IM5TVbFbRaf6v33cecAg9Ai++kiAsJv0JaiuE+rq5/ZW3N6849h61Ci25 HFssCqXZPgLB6qJ458YDeMzqLq51+NcuOW+v9rEzP8pL3NfXd/2a2c1/2EJlaM0x+MTP bXAUv4v1r3IHXTsG7DYObexZB9NgfZnW6a2yiH+5hPy9hg4YUbQ/14X4rPxVB/WkTgiZ xxDgYdIWSi52cz6Xo+RCjfrZlMhzTSKWbZ0UFavHNZZkGiarAXGbbTXz0GLJknrQz0ur 1CYg== X-Forwarded-Encrypted: i=1; AJvYcCVjqYlj2Ia8DiJri0gRf8FYcQBg8idqqq7qXrmBPxgZAulckZpeou1bD0vKA7ztPyX01+v5hb7DCNNTQPfgrzaf@lists.infradead.org X-Gm-Message-State: AOJu0YwUwsDTO2FR6Cj2KJQlHILwwrBMG9Gv87ONGu6d40NvxPKFZMuu xIkUWt+aipBmcK+JVsol0hITVAC41igjVwBoGrMt6I9k5NcuDJTYso0rk18PRnO07uhM0If2xUZ o5w== X-Google-Smtp-Source: AGHT+IHjBDWncMa0JFzAVRBZvunVV3/xf27Bk1UBfEqTh/oBWIS4ZrnlqS4ID0HplL23Cxhn09935A== X-Received: by 2002:a05:6402:51c8:b0:5c2:62c8:30a with SMTP id 4fb4d7f45d1cf-5c262c80401mr55276a12.1.1725269398075; Mon, 02 Sep 2024 02:29:58 -0700 (PDT) Received: from google.com (109.36.187.35.bc.googleusercontent.com. [35.187.36.109]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8989021960sm532554566b.79.2024.09.02.02.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 02:29:57 -0700 (PDT) Date: Mon, 2 Sep 2024 09:29:53 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: acpica-devel@lists.linux.dev, Hanjun Guo , iommu@lists.linux.dev, Joerg Roedel , Kevin Tian , kvm@vger.kernel.org, Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , "Rafael J. Wysocki" , Robert Moore , Robin Murphy , Sudeep Holla , Will Deacon , Alex Williamson , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameerali Kolothum Thodi Subject: Re: [PATCH v2 2/8] iommu/arm-smmu-v3: Use S2FWB when available Message-ID: References: <0-v2-621370057090+91fec-smmuv3_nesting_jgg@nvidia.com> <2-v2-621370057090+91fec-smmuv3_nesting_jgg@nvidia.com> <20240830164019.GU3773488@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240830164019.GU3773488@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_023000_075162_50484CD7 X-CRM114-Status: GOOD ( 32.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 30, 2024 at 01:40:19PM -0300, Jason Gunthorpe wrote: > On Fri, Aug 30, 2024 at 03:12:54PM +0000, Mostafa Saleh wrote: > > > + /* > > > + * If for some reason the HW does not support DMA coherency then using > > > + * S2FWB won't work. This will also disable nesting support. > > > + */ > > > + if (FIELD_GET(IDR3_FWB, reg) && > > > + (smmu->features & ARM_SMMU_FEAT_COHERENCY)) > > > + smmu->features |= ARM_SMMU_FEAT_S2FWB; > > I think that’s for the SMMU coherency which in theory is not related to the > > master which FWB overrides, so this check is not correct. > > Yes, I agree, in theory. > > However the driver today already links them together: > > case IOMMU_CAP_CACHE_COHERENCY: > /* Assume that a coherent TCU implies coherent TBUs */ > return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; > > So this hunk was a continuation of that design. > > > What I meant in the previous thread that we should set FWB only for coherent > > masters as (in attach s2): > > if (smmu->features & ARM_SMMU_FEAT_S2FWB && dev_is_dma_coherent(master->dev) > > // set S2FWB in STE > > I think as I explained in that thread, it is not really correct > either. There is no reason to block using S2FWB for non-coherent > masters that are not used with VFIO. The page table will still place > the correct memattr according to the IOMMU_CACHE flag, S2FWB just > slightly changes the encoding. It’s not just the encoding that changes, as - Without FWB, stage-2 combine attributes - While with FWB, it overrides them. So a cacheable mapping in stage-2 can lead to a non-cacheable (or with different cachableitiy attributes) transaction based on the input. I am not sure though if there is such case in the kernel. Also, that logic doesn't only apply to VFIO, but also for stage-2 only SMMUs that use stage-2 for kernel DMA. > > For VFIO, non-coherent masters need to be blocked from VFIO entirely > and should never get even be allowed to get here. > > If anything should be changed then it would be the above > IOMMU_CAP_CACHE_COHERENCY test, and I don't know if > dev_is_dma_coherent() would be correct there, or if it should do some > ACPI inspection or what. I agree, I believe that this assumption is not accurate, I am not sure what is the right approach here, but in concept I think we shouldn’t enable FWB for non-coherent devices (using dev_is_dma_coherent() or other check) Thanks, Mostafa > > So let's drop the above hunk, it already happens implicitly because > VFIO checks it via IOMMU_CAP_CACHE_COHERENCY and it makes more sense > to put the assumption in one place. > > Thanks, > Jason