Re: [PATCH 08/11] misc: rp1: RaspberryPi RP1 misc driver

Bjorn Helgaas
2024-08-21T16:57:52Z

On Tue, Aug 20, 2024 at 04:36:10PM +0200, Andrea della Porta wrote:
> The RaspberryPi RP1 is ia PCI multi function device containing

s/ia/a/

> peripherals ranging from Ethernet to USB controller, I2C, SPI
> and others.

Add blank lines between paragraphs.

> Implement a bare minimum driver to operate the RP1, leveraging
> actual OF based driver implementations for the on-borad peripherals

s/on-borad/on-board/

> by loading a devicetree overlay during driver probe.
> The peripherals are accessed by mapping MMIO registers starting
> from PCI BAR1 region.
> As a minimum driver, the peripherals will not be added to the
> dtbo here, but in following patches.

> +config MISC_RP1
> + tristate "RaspberryPi RP1 PCIe support"
> + depends on PCI && PCI_QUIRKS
> + select OF
> + select OF_OVERLAY
> + select IRQ_DOMAIN
> + select PCI_DYNAMIC_OF_NODES
> + help
> + Support for the RP1 peripheral chip found on Raspberry Pi 5 board.
> + This device supports several sub-devices including e.g. Ethernet controller,
> + USB controller, I2C, SPI and UART.
> + The driver is responsible for enabling the DT node once the PCIe endpoint
> + has been configured, and handling interrupts.
> + This driver uses an overlay to load other drivers to support for RP1
> + internal sub-devices.

s/support for/support/

Add blank lines between paragraphs. Consider wrapping to fit in 80
columns. Current width of 86 seems random.

> diff --git a/drivers/misc/rp1/Makefile b/drivers/misc/rp1/Makefile
> new file mode 100644
> index 000000000000..e83854b4ed2c
> --- /dev/null
> +++ b/drivers/misc/rp1/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +rp1-pci-objs := rp1-pci.o rp1-pci.dtbo.o
> +obj-$(CONFIG_MISC_RP1) += rp1-pci.o
> diff --git a/drivers/misc/rp1/rp1-pci.c b/drivers/misc/rp1/rp1-pci.c
> new file mode 100644
> index 000000000000..a6093ba7e19a
> --- /dev/null
> +++ b/drivers/misc/rp1/rp1-pci.c
> @@ -0,0 +1,333 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018-22 Raspberry Pi Ltd.

s/22/24/ ?

> +#define RP1_B0_CHIP_ID 0x10001927
> +#define RP1_C0_CHIP_ID 0x20001927

Drop; both unused.

> +#define RP1_PLATFORM_ASIC BIT(1)
> +#define RP1_PLATFORM_FPGA BIT(0)

Drop; both unused.

> +#define RP1_SYSCLK_RATE 200000000
> +#define RP1_SYSCLK_FPGA_RATE 60000000

Drop; both unused.

> +enum {
> + SYSINFO_CHIP_ID_OFFSET = 0,
> + SYSINFO_PLATFORM_OFFSET = 4,
> +};

Drop; unused.

> +/* MSIX CFG registers start at 0x8 */

s/MSIX/MSI-X/

> +#define MSIX_CFG_TEST BIT(1)

Unused.

> +#define INTSTATL 0x108
> +#define INTSTATH 0x10c

Drop; both unused.

> +static void dump_bar(struct pci_dev *pdev, unsigned int bar)
> +{
> + dev_info(&pdev->dev,
> + "bar%d len 0x%llx, start 0x%llx, end 0x%llx, flags, 0x%lx\n",

%pR does most of this for you.

> +static int rp1_irq_set_type(struct irq_data *irqd, unsigned int type)
> +{
> + struct rp1_dev *rp1 = irqd->domain->host_data;
> + unsigned int hwirq = (unsigned int)irqd->hwirq;
> + int ret = 0;
> +
> + switch (type) {
> + case IRQ_TYPE_LEVEL_HIGH:
> + dev_dbg(rp1->dev, "MSIX IACK EN for irq %d\n", hwirq);
> + msix_cfg_set(rp1, hwirq, MSIX_CFG_IACK_EN);
> + rp1->level_triggered_irq[hwirq] = true;
> + break;
> + case IRQ_TYPE_EDGE_RISING:
> + msix_cfg_clr(rp1, hwirq, MSIX_CFG_IACK_EN);
> + rp1->level_triggered_irq[hwirq] = false;
> + break;
> + default:
> + ret = -EINVAL;

If you "return -EINVAL" directly here, I think you can drop "ret" and
just "return 0" below.

> + break;
> + }
> +
> + return ret;
> +}

> +static int rp1_irq_xlate(struct irq_domain *d, struct device_node *node,
> + const u32 *intspec, unsigned int intsize,
> + unsigned long *out_hwirq, unsigned int *out_type)
> +{
> + struct rp1_dev *rp1 = d->host_data;
> + struct irq_data *pcie_irqd;
> + unsigned long hwirq;
> + int pcie_irq;
> + int ret;
> +
> + ret = irq_domain_xlate_twocell(d, node, intspec, intsize,
> + &hwirq, out_type);
> + if (!ret) {
> + pcie_irq = pci_irq_vector(rp1->pdev, hwirq);
> + pcie_irqd = irq_get_irq_data(pcie_irq);
> + rp1->pcie_irqds[hwirq] = pcie_irqd;
> + *out_hwirq = hwirq;
> + }
> +
> + return ret;

if (ret)
return ret;

...
return 0;

would make this easier to read and unindent the normal path.

> + rp1->bar1 = pci_iomap(pdev, 1, 0);

pcim_iomap()

> + if (!rp1->bar1) {
> + dev_err(&pdev->dev, "Cannot map PCI bar\n");

s/bar/BAR/

> +#define PCI_VENDOR_ID_RPI 0x1de4
> +#define PCI_DEVICE_ID_RP1_C0 0x0001

Device ID should include "RPI" as well.