From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26783CA0ED3 for ; Wed, 4 Sep 2024 10:13:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=s2aAiZcms9C9zr6vlSMqqJzOY9QiGj7qPfcxRzT6TOk=; b=Z4I3EF16Y6TO5htdTU8T/ahoOb 8Wm1hV21ubSH+QbYfv0rUMpnTkXAkILuqfObxhFPdHw2YkIP9jPalyckoHuFpfxnhR/VEERUaJF9Q iSzaBR3Y3vmq9me8qrYNWYzNKKXPHnozX5uRwrTadIWoIrj0SXzfqhniUuu7eK1rEEePpi2Ua14m+ hNK6gzhLKZ1TdPfZrv8uGrcuzCdmqQW3t0b1VHBsIAPWwWEk2SDPXkiibdTC8UdpTMCyq/UoqlN95 BwBCqlnX826Xs6+ydWY2ipE0j47zFqNGBWA3Q/RlBlg74YhNChzKz0tVTKz3GjtRE2I53wizsdeQx +d+mpcyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sln0X-00000003r30-06cs; Wed, 04 Sep 2024 10:13:01 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slmTV-00000003ilM-47o6 for linux-arm-kernel@lists.infradead.org; Wed, 04 Sep 2024 09:38:55 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id EA5115C5496; Wed, 4 Sep 2024 09:38:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00C31C4CEC2; Wed, 4 Sep 2024 09:38:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725442733; bh=KmyA68nzsmKeQqVYQzVFeMOcA8YdDjGJMWH0cfv8O4A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=IeBLCiIRh8c4VREeW7bQWZzbnGPRve49Ue8NudWmF/yIRW7kCkUZjRO5lJTE1Q1uY EZWFSZWwesMfu58MDUxRT73RsyShqjpSz5Q4xMeeU4uTnv8E6+It2IM7cKgJSsORbw K2VYXsjxEB8rq9o1ltg1CzHBGfQXSsD0e+dtfNq83DNSvNxqZSl5N6kzQzYGoAAhMU OEiZFNTwa63R0EzMogWoaKG/zDu82Rj4MpbYe9puFToZostf2fatOBDyxsDkFbtfzU aokbdGriHqhn8Q2ds9hTIDfRkCYcyRStjSEpmDl2Oo1vHkbCSD1y+rE1WGnXA1Ty1E O76ouKvPzex1A== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1slmTl-0000000020w-0ZZs; Wed, 04 Sep 2024 11:39:09 +0200 Date: Wed, 4 Sep 2024 11:39:09 +0200 From: Johan Hovold To: manivannan.sadhasivam@linaro.org Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jingoo Han , Chuanhua Lei , Marek Vasut , Yoshihiro Shimoda , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, abel.vesa@linaro.org, johan+linaro@kernel.org, Shashank Babu Chinta Venkata Subject: Re: [PATCH v6 3/4] PCI: qcom: Add equalization settings for 16.0 GT/s Message-ID: References: <20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org> <20240904-pci-qcom-gen4-stability-v6-3-ec39f7ae3f62@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240904-pci-qcom-gen4-stability-v6-3-ec39f7ae3f62@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240904_023854_136468_1B71D6FA X-CRM114-Status: GOOD ( 18.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 04, 2024 at 12:41:59PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > From: Shashank Babu Chinta Venkata > > During high data transmission rates such as 16.0 GT/s, there is an > increased risk of signal loss due to poor channel quality and interference. > This can impact receiver's ability to capture signals accurately. Hence, > signal compensation is achieved through appropriate lane equalization > settings at both transmitter and receiver. This will result in increased > PCIe signal strength. > > Signed-off-by: Shashank Babu Chinta Venkata > Reviewed-by: Manivannan Sadhasivam > [mani: dropped the code refactoring and minor changes] > Signed-off-by: Manivannan Sadhasivam > +#define GEN3_EQ_CONTROL_OFF 0x8a8 Nit: uppercase hex since that's what is used for the other offsets > +#define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0) > +#define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE BIT(4) > +#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC GENMASK(23, 8) > +#define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL BIT(24) > + > +#define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8ac Nit: odd indentation uses spaces, uppercase > +#define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0) > +#define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5) > +#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA GENMASK(13, 10) > +#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA GENMASK(17, 14) > + > #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 > #define PORT_MLTI_UPCFG_SUPPORT BIT(7) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c > new file mode 100644 > index 000000000000..dc7d93db9dc5 > --- /dev/null > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c > @@ -0,0 +1,45 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > + > +#include "pcie-designware.h" > +#include "pcie-qcom-common.h" > + > +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci) > +{ > + u32 reg; > + > + /* > + * GEN3_RELATED_OFF register is repurposed to apply equalization > + * settings at various data transmission rates through registers namely > + * GEN3_EQ_*. RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF determines > + * data rate for which this equalization settings are applied. *The* RATE_SHADOW_SEL bit field *the* data rate s/this/these/ > + */ > + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; > + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, 0x1); How does 0x1 map to gen4/16 GT? > + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); > + > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); > + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | > + GEN3_EQ_FMDC_N_EVALS | > + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | > + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); > + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | > + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); > + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); > + > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); > + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | > + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | > + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | > + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > +} > +EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings); > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h > new file mode 100644 > index 000000000000..259e04b7bdf9 > --- /dev/null > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.h > @@ -0,0 +1,8 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include "pcie-designware.h" You only need a forward declaration: struct dw_pcie; > + > +void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci); Compile guard still missing. Johan