From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECF44CD3431 for ; Wed, 4 Sep 2024 10:19:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QPFHK4rR/yP/s1rTJ6nvyM5JkozHCmthjc3ojCxE+Jw=; b=J+T48l/SN0+z0WjKFxUgFZSTeK 4BWhrbNiyabEIh7B7GgqNU/b1M85fKZ5mFOmOSCRgreU5PdnrbMML5YLv/DJnKkple1FmzseegKkj fylDre7yrH0BayFZR9RHLbVWphclph28Y4bnj8fzEI6cOXCHOWPfj0HWO3Mw7w9b6z3yCtUFPi0A5 rZ2IpycfHJ+LRZIa0azBFXHD+WXkRILzTPjZu+hQGtZYF0D5bEI4XI0NLFfltMBMCQ+3RtyVGfk3o Z1YuZUqehYWT+KirXp8iajnLg2THAzjE2eOVMKFVwid4RDk+4bOiwiYhTp2jNRC7g5elMSDo2cfhe FAO2AUcQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sln71-00000003sPj-12xU; Wed, 04 Sep 2024 10:19:43 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slmhb-00000003mNf-0gS8 for linux-arm-kernel@lists.infradead.org; Wed, 04 Sep 2024 09:53:28 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 1F3F9A432B0; Wed, 4 Sep 2024 09:53:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E849DC4CEC2; Wed, 4 Sep 2024 09:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725443606; bh=Rs/7CNs57mYMKC518TOwDxf97qBOBf04kquglQP1lwc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=UsSlsSskbJHuC+h8APdYWUHWE27EWWoS5s+VzmxiB2D3IPWTRipWpIKtn5zyni497 hVP+Ox7LqqiXOGEFtPsrAJZdEExcCBqzCxaqqgOE3kpzKjfJRZsoFGT29mYI8m5Iqw rZ0zCfCTVztes5x+XnObG6NHo9bJwDiCtpeflbGcddmKgwqEpCu6SF/qpHVPh9ni1W ppDs8jvB+vds1Aih5gTRYLgyGZ/opjK/46+emlH4fin2rM9HKedQuMGGy+q3a8UKng bPzCsVAgywe3ywpnlWsmkHQ8qY0/f+totvXZS/nscbccko+yJ9Z0oBge2FV1+Fh4PX GGhZptjpW3lFg== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1slmhq-000000002Dc-0ROQ; Wed, 04 Sep 2024 11:53:42 +0200 Date: Wed, 4 Sep 2024 11:53:42 +0200 From: Johan Hovold To: manivannan.sadhasivam@linaro.org Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jingoo Han , Chuanhua Lei , Marek Vasut , Yoshihiro Shimoda , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, abel.vesa@linaro.org, johan+linaro@kernel.org, Shashank Babu Chinta Venkata Subject: Re: [PATCH v6 4/4] PCI: qcom: Add RX margining settings for 16.0 GT/s Message-ID: References: <20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org> <20240904-pci-qcom-gen4-stability-v6-4-ec39f7ae3f62@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240904-pci-qcom-gen4-stability-v6-4-ec39f7ae3f62@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240904_025327_359891_60312E08 X-CRM114-Status: GOOD ( 18.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 04, 2024 at 12:42:00PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > From: Shashank Babu Chinta Venkata > > Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These > settings improve link stability while operating at high date rates and > helps to improve signal quality. > > Signed-off-by: Shashank Babu Chinta Venkata > Reviewed-by: Manivannan Sadhasivam > [mani: dropped the code refactoring and minor changes] > Signed-off-by: Manivannan Sadhasivam > --- > drivers/pci/controller/dwc/pcie-designware.h | 18 ++++++++++++++++ > drivers/pci/controller/dwc/pcie-qcom-common.c | 31 +++++++++++++++++++++++++++ > drivers/pci/controller/dwc/pcie-qcom-common.h | 1 + > drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++- > drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- > 5 files changed, 56 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 51744ad25575..f5be99731f7e 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -209,6 +209,24 @@ > > #define PCIE_PL_CHK_REG_ERR_ADDR 0xB28 > > +/* > + * 16.0 GT/s (GEN4) lane margining register definitions nit: Gen 4? > + */ > +#define GEN4_LANE_MARGINING_1_OFF 0xb80 nit: upper case hex > +#define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24) > +#define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16) > +#define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8) > +#define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0) > + > +#define GEN4_LANE_MARGINING_2_OFF 0xb84 Same here > +#define MARGINING_IND_ERROR_SAMPLER BIT(28) > +#define MARGINING_SAMPLE_REPORTING_METHOD BIT(27) > +#define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26) > +#define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25) > +#define MARGINING_VOLTAGE_SUPPORTED BIT(24) > +#define MARGINING_MAXLANES GENMASK(20, 16) > +#define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8) > +#define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0) > /* > * iATU Unroll-specific register definitions > * From 4.80 core version the address translation will be made by unroll > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c > index dc7d93db9dc5..99b75e7f085d 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-common.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c > @@ -43,3 +43,34 @@ void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci) > dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > } > EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings); > + > +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci) I'd try to find a shorter symbol name here, "settings" seems redundant after "set". Perhaps just qcom_pcie_common_enable_lane_margining() or qcom_pcie_common_enable_16gt_lane_margining()? if these settings are indeed specific to 16 GT/s. But perhaps it's better to let the helper honour pci->max_link_speed if different settings will later be needed for higher speeds: if (pcie_link_speed[pci->max_link_speed] >= PCIE_SPEED_16_0GT) qcom_pcie_common_enable_lane_margining(pci) > void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci); > +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci); And maybe something similar for the eq settings for symmetry. Johan