From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38931CE7AFD for ; Fri, 6 Sep 2024 10:03:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To: Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=nqOto8ket8AGXnTysiKRFyOgh2uR/XlInO+fheQGL00=; b=3afHp7U9kS+xtBrkCcURXZyPn0 b7J7I3XB5hoYZ11PuKeStQpMWUX1MQqgBQ4ZSSpLgy6l848uHOIVgAMC5xcRFx+hZw+1Xiir11CCM N5wQYQIrCt2GkWgxDDOzU4pyz4utfZJK2m+3ahi1GXX4Di3RGSQqtaSeLAZZykyhV32p+B2Wwzhqg nY4e2JeMTxzs3VKIH0LWP1YChDlT6/bfgW5Lkin1jNYYFnEnXfO14YElH6pTs2U3MhfT2CPr/orNp ybApBSNGPomhAsOFhf1IKmR6/x5Vj9nLmsF08acbXF1VBaAtGfRY6s5dMr5/os3HI+tXucw+fEJw3 EgCRqV8A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1smVoe-0000000BfPF-2qJO; Fri, 06 Sep 2024 10:03:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1smVWH-0000000BaA8-3YYc for linux-arm-kernel@lists.infradead.org; Fri, 06 Sep 2024 09:44:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 427BDFEC; Fri, 6 Sep 2024 02:45:12 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D281E3F73F; Fri, 6 Sep 2024 02:44:43 -0700 (PDT) Date: Fri, 6 Sep 2024 10:44:41 +0100 From: Mark Rutland To: Tian Tao Cc: catalin.marinas@arm.com, will@kernel.org, jonathan.cameron@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linuxarm@huawei.com Subject: Re: [PATCH] arm64: Add ARM64_HAS_LSE2 CPU capability Message-ID: References: <20240906090812.249473-1-tiantao6@hisilicon.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240906090812.249473-1-tiantao6@hisilicon.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240906_024446_010378_87291D1C X-CRM114-Status: GOOD ( 26.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 06, 2024 at 05:08:12PM +0800, Tian Tao wrote: > When FEAT_LSE2 is implemented and Bit 6 of sctlr_elx is nAA, the > full name of the Not-aligned access. nAA bit has two values: > 0b0 Unaligned accesses by the specified instructions generate an > Alignment fault. > 0b1 Unaligned accesses by the specified instructions do not generate > an Alignment fault. > > this patch sets the nAA bit to 1,The following instructions will not > generate an Alignment fault if all bytes being accessed are not within > a single 16-byte quantity: > • LDAPR, LDAPRH, LDAPUR, LDAPURH, LDAPURSH, LDAPURSW, LDAR, LDARH,LDLAR, > LDLARH. > • STLLR, STLLRH, STLR, STLRH, STLUR, and STLURH > > Signed-off-by: Tian Tao What is going to depend on this? Nothing in the kernel depends on being able to make unaligned accesses with these instructions, and (since you haven't added a HWCAP), userspace has no idea that these accesses won't generate an alignment fault. Mark. > --- > arch/arm64/Kconfig | 10 ++++++++++ > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kernel/cpufeature.c | 18 ++++++++++++++++++ > arch/arm64/tools/cpucaps | 1 + > 4 files changed, 30 insertions(+) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 77d7ef0b16c2..7afe73ebcd79 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -2023,6 +2023,16 @@ config ARM64_TLB_RANGE > The feature introduces new assembly instructions, and they were > support when binutils >= 2.30. > > +config ARM64_LSE2_NAA > + bool "Enable support for not-aligned access" > + depends on AS_HAS_ARMV8_4 > + help > + LSE2 is an extension to the original LSE (Large System Extensions) feature, > + introduced in ARMv8.4. > + > + Enable this feature will not generate an Alignment fault if all bytes being > + accessed are not within a single 16-byte quantity. > + > endmenu # "ARMv8.4 architectural features" > > menu "ARMv8.5 architectural features" > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 8cced8aa75a9..42e3a1959aa8 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -854,6 +854,7 @@ > #define SCTLR_ELx_ENDB (BIT(13)) > #define SCTLR_ELx_I (BIT(12)) > #define SCTLR_ELx_EOS (BIT(11)) > +#define SCTLR_ELx_nAA (BIT(6)) > #define SCTLR_ELx_SA (BIT(3)) > #define SCTLR_ELx_C (BIT(2)) > #define SCTLR_ELx_A (BIT(1)) > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 646ecd3069fd..558869a7c7f0 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2299,6 +2299,14 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) > } > #endif /* CONFIG_ARM64_MTE */ > > +#ifdef CONFIG_ARM64_LSE2_NAA > +static void cpu_enable_lse2(const struct arm64_cpu_capabilities *__unused) > +{ > + sysreg_clear_set(sctlr_el2, SCTLR_ELx_nAA, SCTLR_ELx_nAA); > + isb(); > +} > +#endif > + > static void user_feature_fixup(void) > { > if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { > @@ -2427,6 +2435,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) > }, > #endif /* CONFIG_ARM64_LSE_ATOMICS */ > +#ifdef CONFIG_ARM64_LSE2_NAA > + { > + .desc = "Support for not-aligned access", > + .capability = ARM64_HAS_LSE2, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .matches = has_cpuid_feature, > + .cpu_enable = cpu_enable_lse2, > + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, AT, IMP) > + }, > +#endif > { > .desc = "Virtualization Host Extensions", > .capability = ARM64_HAS_VIRT_HOST_EXTN, > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index ac3429d892b9..0c7c0a293574 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -41,6 +41,7 @@ HAS_HCX > HAS_LDAPR > HAS_LPA2 > HAS_LSE_ATOMICS > +HAS_LSE2 > HAS_MOPS > HAS_NESTED_VIRT > HAS_PAN > -- > 2.33.0 > >