From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0712C3ABA2 for ; Mon, 16 Sep 2024 15:32:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uzTOD8o5X6LdK4UiGjUllKRySkE78VpK9ZS8WHJbWIY=; b=TgcSfSZYxqVFYouYxVZtNtOUNI AqdDOF2dGB8QmIUOfGKRxGW8PvTbjKVDxvn54W+GdhMKBVsaxV5wp5g2GlKFNth56FpgMolh5/0+e nvpS58R3fLmSF6pzE8GOVpch5sNroXJeNE+oUcnykXisUNiIYR037z//5WBA5w9VtICJsYG3+l1Re Oik9VoQFEbEBq1Jb+z6gIeC2PT/2H/dq6tSAZvF4X6AQXnjKu6pojI8ZVOUTlPErhCUrP1xeFuwuR NwKrOpkncB5WTgvVsW7lKtYoiemjzPnxLkMZKtLsLte0VldNju4rtBd9CRmLINQ8XkIa4VGDwW6tC NrPNLR8w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sqDhh-00000004M6i-35Dy; Mon, 16 Sep 2024 15:31:53 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sqDgc-00000004M2e-07fM for linux-arm-kernel@lists.infradead.org; Mon, 16 Sep 2024 15:30:47 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id AD6165C5B33; Mon, 16 Sep 2024 15:30:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6DA1C4CEC4; Mon, 16 Sep 2024 15:30:43 +0000 (UTC) Date: Mon, 16 Sep 2024 16:30:41 +0100 From: Catalin Marinas To: Nick Chan Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, Marc Zyngier Subject: Re: [PATCH v2 2/2] arm64: cpufeature: Pretend that Apple A10 family does not support 32-bit EL0 Message-ID: References: <20240909091425.16258-1-towinchenmi@gmail.com> <20240909091425.16258-3-towinchenmi@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240916_083046_299182_9DD8972E X-CRM114-Status: GOOD ( 19.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Sep 16, 2024 at 09:41:12PM +0800, Nick Chan wrote: > On 9/9/2024 17:10, Nick Chan wrote: > > The Apple A10 family consists of physical performance and efficiency > > cores, and only one of them can be active at a given time depending on > > the current p-state. However, only the performance cores can execute > > 32-bit EL0. This results in logical cores that can only execute 32-bit > > EL0 in high p-states. > > Further research shows that the MPIDR_EL1 values between the two core > types are different. And whether the two core type have any extra > differences is anyone's guess right now. So far, nothing seems to break > horribly without special workarounds for the MPIDR value (with cpufreq > enabled downstream) as: > 1. There are no KVM, GIC, ACPI, PSCI or cpuidle > 2. All CPUs switch P-mode and E-mode together > > However, all of this is broken enough that this piece of code should go > into arch/arm64/kernel/cpu_errata.c, and also generate a > TAINT_CPU_OUT_OF_SPEC for these cursed CPUs. I wouldn't carry any additional logic in the kernel for such configuration (long time ago Arm had something similar, the big.LITTLE switcher, but the CPUs were fairly similar from a feature perspective). > > Trying to support 32-bit EL0 on a CPU that can only execute it in certain > > states is a bad idea. The A10 family only supports 16KB page size anyway > > so many AArch32 executables won't run anyways. Pretend that it does not > > support 32-bit EL0 at all. CONFIG_COMPAT depends on ARM64_4K_PAGES || EXPERT. Do we really need these patches in case one enables EXPERT and tries to run 32-bit binaries that never ran on 16K pages before? -- Catalin