From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 719CECF9C71 for ; Mon, 23 Sep 2024 21:30:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Msr4e2aktGMwp7wsjBm8wr8s1DK/j+37ksdEXI7Qv90=; b=c15o4dPr3/JCPKo4uSD/qOYv9o a3/I2zH4PxNTCwCQ9/EBhTx0yk7vFT2RklTHujdbYfDKMpaF3Qm2LtiOcoeWbyeFZvwwPKX1DsBA/ aqvEtSWWrE90zW/h6SXklDWE84GZGrnm5eSbwsVzweiu4wwAhg1gaK79KvhXN/wh0OpI2fcmEhDmr KJYZsbB4G3R4gm5z1PWW1OnRVQyIKJSxZZiUCw/MbmmXVPRDDDfieNKacTN0sAjMwxVp+sFUSzUPY hxxmaUE82ZzMsDrPKyjNxQVtCuFZ0fNCVRT6xw7lJy2CBAz9I5/ygElVwDadui13phRpDE1jgKykZ auvyrGAA==; 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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="CeZNBjXD8FkiuUtc" Content-Disposition: inline In-Reply-To: <20240923171041.GA1158802@bhelgaas> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240923_142923_764290_345D0C12 X-CRM114-Status: GOOD ( 30.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --CeZNBjXD8FkiuUtc Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > On Fri, Sep 20, 2024 at 10:26:28AM +0200, Lorenzo Bianconi wrote: > > The PCIe controller available on the EN7581 SoC does not support reset > > via the following lines: > > - PCIE_MAC_RSTB > > - PCIE_PHY_RSTB > > - PCIE_BRG_RSTB > > - PCIE_PE_RSTB > >=20 > > Introduce the reset callback in order to avoid resetting the PCIe port > > for Airoha EN7581 SoC. > >=20 > > Tested-by: Hui Ma > > Signed-off-by: Lorenzo Bianconi > > --- > > drivers/pci/controller/pcie-mediatek-gen3.c | 44 ++++++++++++++++++---= -------- > > 1 file changed, 28 insertions(+), 16 deletions(-) > >=20 > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/= controller/pcie-mediatek-gen3.c > > index 5c19abac74e8..9cea67e92d98 100644 > > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > @@ -128,10 +128,12 @@ struct mtk_gen3_pcie; > > /** > > * struct mtk_gen3_pcie_pdata - differentiate between host generations > > * @power_up: pcie power_up callback > > + * @reset: pcie reset callback > > * @phy_resets: phy reset lines SoC data. > > */ > > struct mtk_gen3_pcie_pdata { > > int (*power_up)(struct mtk_gen3_pcie *pcie); > > + void (*reset)(struct mtk_gen3_pcie *pcie); > > struct { > > const char *id[MAX_NUM_PHY_RESETS]; > > int num_resets; > > @@ -373,6 +375,28 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pc= ie *pcie) > > writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); > > } > > =20 > > +static void mtk_pcie_reset(struct mtk_gen3_pcie *pcie) > > +{ > > + u32 val; > > + > > + /* Assert all reset signals */ > > + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); > > + val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; > > + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); > > + > > + /* > > + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) > > + * and 2.2.1 (Initial Power-Up (G3 to S0)). > > + * The deassertion of PERST# should be delayed 100ms (TPVPERL) > > + * for the power and clock to become stable. > > + */ > > + msleep(100); >=20 > I see you're just moving this, but it's a good chance to use > PCIE_T_PVPERL_MS. ack, I will add it. >=20 > > + > > + /* De-assert reset signals */ > > + val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RS= TB); > > + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); > > +} > > + > > static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) > > { > > struct resource_entry *entry; > > @@ -402,22 +426,9 @@ static int mtk_pcie_startup_port(struct mtk_gen3_p= cie *pcie) > > val |=3D PCIE_DISABLE_DVFSRC_VLT_REQ; > > writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); > > =20 > > - /* Assert all reset signals */ > > - val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); > > - val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; > > - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); > > - > > - /* > > - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) > > - * and 2.2.1 (Initial Power-Up (G3 to S0)). > > - * The deassertion of PERST# should be delayed 100ms (TPVPERL) > > - * for the power and clock to become stable. > > - */ > > - msleep(100); > > - > > - /* De-assert reset signals */ > > - val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RS= TB); > > - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); > > + /* Reset the PCIe port if requested by the hw */ >=20 > I don't see any real "request" from the hardware. IIUC, this is more > like "assert reset if this hardware supports it". ack, %s/requested/supported. I will fix it. Regards, Lorenzo >=20 > > + if (pcie->soc->reset) > > + pcie->soc->reset(pcie); > > =20 > > /* Check if the link is up or not */ > > err =3D readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, > > @@ -1207,6 +1218,7 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = =3D { > > =20 > > static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 =3D { > > .power_up =3D mtk_pcie_power_up, > > + .reset =3D mtk_pcie_reset, > > .phy_resets =3D { > > .id[0] =3D "phy", > > .num_resets =3D 1, > >=20 > > --- > > base-commit: f2024903cb387971abdbc6398a430e735a9b394c > > change-id: 20240920-pcie-en7581-rst-fix-8161658c13c4 > >=20 > > Best regards, > > --=20 > > Lorenzo Bianconi > >=20 --CeZNBjXD8FkiuUtc Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTquNwa3Txd3rGGn7Y6cBh0uS2trAUCZvHdrgAKCRA6cBh0uS2t rEONAP4qiHrP6to/gC9PCjS4UG9xJ16SJrG/IlXBo0VmZrPJtAD7B2K8bXfQksAS +/PGKL0/4VYtA7fNZEnlTYRxqoOQVw0= =OoIH -----END PGP SIGNATURE----- --CeZNBjXD8FkiuUtc--