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Thu, 26 Sep 2024 23:32:11 -0700 Date: Thu, 26 Sep 2024 23:32:10 -0700 From: Nicolin Chen To: Yi Liu CC: , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 00/19] iommufd: Add VIOMMU infrastructure (Part-1) Message-ID: References: <82632802-c55a-4199-b685-8b594a8e7104@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|DS7PR12MB5792:EE_ X-MS-Office365-Filtering-Correlation-Id: d71aa1d9-9ac6-453b-9528-08dcdebe2841 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?O96ifY1zdApHyjT5kYXjrDbN2aE3QIfscyIq9Mq4n3X6a/Hbka03Q/FyuIBq?= =?us-ascii?Q?wo/AkXv5dFzrT4ARiO7x9SIzh6W+i9QtBJJp++ELTIA1OK3F+VBFpP3lpsmF?= =?us-ascii?Q?cQhdXuqq8AfvV4dxahj4aFUD/zrVSXsc0y7QIJlivMQe/MzHnJV7tGLy88Sb?= =?us-ascii?Q?BszKP7Gx3mf/LyM/lqqUTex/Sx2J21G4GS6oqrUWXVS2uDhkDUJIDgELgTi/?= =?us-ascii?Q?EHEOsp1Zr5xECHU6OFamL03UB3GOlju0djFMN6Jhu4hnRcCMAxK6K8pjKh0Z?= =?us-ascii?Q?BpRsb7xVcdlVjAlHxWAkuGLqwyat5VuX/NR+GRmJaGi8BsmjwrjN4EmRt42U?= =?us-ascii?Q?1ICD5c25GQ5BpQ/CRuQa/hHZ1j0z79DWWossK4rzP8mAXgLIDpmDRMhDWInu?= =?us-ascii?Q?VqiE0Xugr8nxvmSe94iyi7a48aipfevcDLglniDHts6pxuUbZYfAj93bXsua?= =?us-ascii?Q?O8KtUAtyHGVMKIUrrVme7qGoqVyFXCmpA8pYVnWGPNuxHATmFN/mAzswFq1o?= =?us-ascii?Q?oSIAw5jjJWCLhU1ZqBiSuVhrf42Q4VWmKudG1M7KCilKK50A3IO2/QV4wxCI?= =?us-ascii?Q?ROUQvB/ijgW22runUq2Vg3aTMKjjD2VKa5IhmuedRzxovFiSjX8SUmSsnOIF?= =?us-ascii?Q?0RRPt1/XYDkZleuLAZHM/csWpTEr0BYXbBbil80DNIlyTMYOCmY60/UaS04A?= =?us-ascii?Q?8GcTs7Zf2hdOzFkPI545NIca9ScIZuYrwvBIUBSsgma4sppGND3hId4FbZ1E?= =?us-ascii?Q?W+vu4wcONMPSTm0iyYDsugQaIvGIqNXUxNrM1mwH4LBjxVk2/mz6WCMEgfdx?= =?us-ascii?Q?8bO7ESMhCITWuh8sVjQLy9q543c7WgSgAqT5lmmPP09nVFnuVbWm2evkzt15?= =?us-ascii?Q?iXINBXLECTVz8k/rYeMvLNMO9Csqp8FQOFtpukRiA5RCBftrDEec/QoimDVK?= =?us-ascii?Q?vwAJi9OmN5Pw6SL02X4/hcHktCDzvlwrbnJel1nrcRR7TnJU07FG6FY45twh?= =?us-ascii?Q?6QHSI4Xso58ZqB/fnCHMtCwQw9cgRvKwIbY1o1EFbBaYoueJoLhQv2I+DIkV?= =?us-ascii?Q?j/Hm6TmQL7096PAIknCxv0x9CESQtowAiTpLKL0cDeZxzRBtSn2ijipied5/?= =?us-ascii?Q?CaqV9i3G3zf5LdDKCGBkmd2j/8Pw9fkhfb6MREGK8yNzzBCFnyEzVVQmD5IN?= =?us-ascii?Q?PqY1PBQQfifdUUNlo/X8qwUrW3RhqoxosaZ2HC16ArK2eF7q5RHen6+fIPIi?= =?us-ascii?Q?jNVyef5votgdveqnwXpft9jkZnGj0f28SMHXpsFmwt8BpT3cj1uwEqAKU0kr?= =?us-ascii?Q?CBd4DN8pOzxFWm+/6owgupoVfAOn3bDvw8rYNE/wxSuM4qIGap3FrYeVpEeQ?= =?us-ascii?Q?OvFLo2SGmzxUwtFHniJF9IAxu4xi?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2024 06:32:27.9056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d71aa1d9-9ac6-453b-9528-08dcdebe2841 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5792 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240926_233236_879649_0D010A51 X-CRM114-Status: GOOD ( 28.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 27, 2024 at 01:54:45PM +0800, Yi Liu wrote: > > > > Baolu told me that Intel may have the same: different domain IDs > > > > on different IOMMUs; multiple IOMMU instances on one chip: > > > > https://lore.kernel.org/linux-iommu/cf4fe15c-8bcb-4132-a1fd-b2c8ddf2731b@linux.intel.com/ > > > > So, I think we are having the same situation here. > > > > > > yes, it's called iommu unit or dmar. A typical Intel server can have > > > multiple iommu units. But like Baolu mentioned in that thread, the intel > > > iommu driver maintains separate domain ID spaces for iommu units, which > > > means a given iommu domain has different DIDs when associated with > > > different iommu units. So intel side is not suffering from this so far. > > > > An ARM SMMU has its own VMID pool as well. The suffering comes > > from associating VMIDs to one shared parent S2 domain. > > Is this because of the VMID is tied with a S2 domain? On ARM, yes. VMID is a part of S2 domain stuff. > > Does a DID per S1 nested domain or parent S2? If it is per S2, > > I think the same suffering applies when we share the S2 across > > IOMMU instances? > > per S1 I think. The iotlb efficiency is low as S2 caches would be > tagged with different DIDs even the page table is the same. :) On ARM, the stage-1 is tagged with an ASID (Address Space ID) while the stage-2 is tagged with a VMID. Then an invalidation for a nested S1 domain must require the VMID from the S2. The ASID may be also required if the invalidation is specific to that address space (otherwise, broadcast per VMID.) I feel these two might act somehow similarly to the two DIDs during nested translations? > > > > Adding another vIOMMU wrapper on the other hand can allow us to > > > > allocate different VMIDs/DIDs for different IOMMUs. > > > > > > that looks like to generalize the association of the iommu domain and the > > > iommu units? > > > > A vIOMMU is a presentation/object of a physical IOMMU instance > > in a VM. > > a slice of a physical IOMMU. is it? Yes. When multiple nested translations happen at the same time, IOMMU (just like a CPU) is shared by these slices. And so is an invalidation queue executing multiple requests. Perhaps calling it a slice sounds more accurate, as I guess all the confusion comes from the name "vIOMMU" that might be thought to be a user space object/instance that likely holds all virtual stuff like stage-1 HWPT or so? > and you treat S2 hwpt as a resource of the physical IOMMU as well. Yes. A parent HWPT (in the old day, we called it "kernel-manged" HWPT) is not a user space thing. This belongs to a kernel owned object. > > This presentation gives a VMM some capability to take > > advantage of some of HW resource of the physical IOMMU: > > - a VMID is a small HW reousrce to tag the cache; > > - a vIOMMU invalidation allows to access device cache that's > > not straightforwardly done via an S1 HWPT invalidation; > > - a virtual device presentation of a physical device in a VM, > > related to the vIOMMU in the VM, which contains some VM-level > > info: virtual device ID, security level (ARM CCA), and etc; > > - Non-PRI IRQ forwarding to the guest VM; > > - HW-accelerated virtualization resource: vCMDQ, AMD VIOMMU; > > might be helpful to draw a diagram to show what the vIOMMU obj contains.:) That's what I plan to. Basically looks like: device---->stage1--->[ viommu [s2_hwpt, vmid, virq, HW-acc, etc.] ] Thanks Nic