[PATCH 4/8] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE

Yao Zi
2024-10-01T04:32:01Z

RK3528 comes with a new PLL type, flagged by ROCKCHIP_PLL_FIXED_MODE,
which should operate in normal mode only. Add corresponding definition
and handle it in code.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
drivers/clk/rockchip/clk-pll.c | 10 ++++++----
drivers/clk/rockchip/clk.h | 2 ++
2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 606ce5458f54..46be1c67301a 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
rockchip_rk3036_pll_get_params(pll, &cur);
cur.rate = 0;

- cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
- if (cur_parent == PLL_MODE_NORM) {
- pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
- rate_change_remuxed = 1;
+ if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
+ if (cur_parent == PLL_MODE_NORM) {
+ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
+ rate_change_remuxed = 1;
+ }
}

/* update pll values */
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index fd3b476dedda..1efc5c3a1e77 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -391,6 +391,7 @@ struct rockchip_pll_rate_table {
* Flags:
* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
* rate_table parameters and ajust them if necessary.
+ * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
*/
struct rockchip_pll_clock {
unsigned int id;
@@ -408,6 +409,7 @@ struct rockchip_pll_clock {
};

#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)

#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
_lshift, _pflags, _rtable) \
--
2.46.0