[PATCH 3/8] dt-bindings: clock: Add rockchip,rk3528-cru

Yao Zi
2024-10-01T04:30:50Z

Document Rockchip RK3528 clock and reset unit.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
.../bindings/clock/rockchip,rk3528-cru.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
new file mode 100644
index 000000000000..ae51dfde5bb9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3528 Clock and Reset Controller
+
+maintainers:
+ - Yao Zi <ziyao@disroot.org>
+
+description: |
+ The RK3528 clock controller generates the clock and also implements a reset
+ controller for SoC peripherals. For example, it provides SCLK_UART0 and
+ PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
+ module.
+ Each clock is assigned an identifier, consumer nodes can use it to specify
+ the clock. All available clock and reset IDs are defined in dt-binding
+ headers.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3528-cru
+
+ reg:
+ maxItems: 1
+
+ assigned-clocks: true
+
+ assigned-clock-rates: true
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: xin24m
+ - const: phy_50m_out
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0xff4a0000 0x30000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.46.0