From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2047FCFC274 for ; Tue, 15 Oct 2024 08:17:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TA16MG/7R5xQpvUXP/XMeAYs+VSbwm9U48Qbuo70jHU=; b=tA3WRSb16Y0K41x589gbdPbGMe lCf7hSulVbqKnWz0WG6IR428eKdIum3b3sgcziQ9a2JgFMm7j9yFmDls9NPxuXptbpzZU5K7DS9z5 Fw+lFhZaL06qWKEigzYYwOvSVOOzfbtidczgipgJckhfKMvJYOVosZM4+Po9G39GrLw8WOX+CkEat +CEqXO8EP8Cf5G4Bkzibt3947ozOcT7fYC1OO1sRQ/wYadtv54u0DMnApjm6dpC3nxaJECErBiZho W6dvV3b0V0PEuxcH604R+I75pS0xDC4ByfM2dg0UNWt6uHnXc+XkNnb7vsSIRtC56EtpDb4AIfr5J /BYl0eFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t0ck5-00000007Tam-3al4; Tue, 15 Oct 2024 08:17:21 +0000 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t0cgU-00000007SxH-2PGY for linux-arm-kernel@lists.infradead.org; Tue, 15 Oct 2024 08:13:39 +0000 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-20ca03687fdso451515ad.0 for ; Tue, 15 Oct 2024 01:13:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1728980017; x=1729584817; darn=lists.infradead.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=TA16MG/7R5xQpvUXP/XMeAYs+VSbwm9U48Qbuo70jHU=; b=CkHSbJOLJCmCUWPImXaHxaVZG3uSGi2K3yZdvr+q5ePDgL+5/q9YBoSQn/kzLJOHoT 71fDO9FK9DyerpagWdTd+QdbiwIbU89+tsTOrBA/T0K+VicP4BuqbPrGZUz2QQcpUCXD V88LgfY9dQgBynwkgBPyMWeW3SWRfOpYSS4p2LltRSK1TRu8/rtU9xRrhg7ojDG8CLft el9QzQp0RzuBlbWmKNeaCRSsFHOe1MA9sRZ5fIO/CIuVchfmPlTEl2BcZNeAnIpyP4Kh RLVHHnv05vxbVjSMp1U6rqfuoexNWRKr7FmqhtyJbg3wI6A3IMRXDFshdAQAkZRYvdv6 PiNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728980017; x=1729584817; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=TA16MG/7R5xQpvUXP/XMeAYs+VSbwm9U48Qbuo70jHU=; b=L9y51EgN1H4Alyt9IaR7vHTXxpjRFDyioxPtK6dVRzh9q7IrGX02KvwvWXK73Fliz+ MsfK8E4vPEV5WDqax/hyrvSMjfec+MBEXyqFycI13MwoDEevm3s8uysm+ucjAqdpwDIq 6LSa326rXtkZVWrBh8EtRQa/lUuB+XjVnvD333UvFqup9WW/GzcTaIGX+cgIVlMCQ26G 3h6XK8tbe4LfO7PZM33iu8TT85PvaAnv5LzDe/sULVopFV/4ni+rEyRe8vFHnUsSRZZ6 YJRZ0ltE9aoAFa58rWWyEL/gePhZuSzeFiuvJN3VlfK0+/WVS4pSXIaoPt3pEzwJh4/8 x4Zw== X-Forwarded-Encrypted: i=1; AJvYcCXgNgmP257tnOUJtxBjUp30p4f4AuSqbBAERaIKkHCx61rQuXjbZHIBASHRjmFrEB5fmn/SiBeBLOylkfqM9iKn@lists.infradead.org X-Gm-Message-State: AOJu0YxK91mJY3yrGs6+5PHWtOsa0TV+NIFC+MDPOLPxddzreySPst77 auHPXOQr4/8PNqjOOUhI/VJr7h1e34Y6FGdeIv3wHZN1QSkW66yvI521WYe8Bw== X-Google-Smtp-Source: AGHT+IFPYSMCddOeaPqNVedMQyNkNHHitiRtEnpSVjBP9NxlbBg1ePA85fokMg2Rqob3akpUMvOQwg== X-Received: by 2002:a17:903:41c8:b0:20b:81bb:4a81 with SMTP id d9443c01a7336-20cc02a3b50mr5194105ad.7.1728980017312; Tue, 15 Oct 2024 01:13:37 -0700 (PDT) Received: from google.com (62.166.143.34.bc.googleusercontent.com. [34.143.166.62]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d17f87cbcsm6978725ad.8.2024.10.15.01.13.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 01:13:36 -0700 (PDT) Date: Tue, 15 Oct 2024 08:13:28 +0000 From: Pranjal Shrivastava To: "Peng Fan (OSS)" Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joy Zou , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Peng Fan , Jason Gunthorpe Subject: Re: [PATCH RFC 2/2] iommu/arm-smmu-v3: Bypass SID0 for NXP i.MX95 Message-ID: References: <20241015-smmuv3-v1-0-e4b9ed1b5501@nxp.com> <20241015-smmuv3-v1-2-e4b9ed1b5501@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241015-smmuv3-v1-2-e4b9ed1b5501@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241015_011338_638984_2BF23A76 X-CRM114-Status: GOOD ( 29.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 15, 2024 at 11:14:43AM +0800, Peng Fan (OSS) wrote: > From: Peng Fan > > i.MX95 eDMA3 connects to DSU ACP, supporting dma coherent memory to > memory operations. However TBU is in the path between eDMA3 and ACP, > need to bypass the default SID 0 to make eDMA3 work properly. > > Signed-off-by: Peng Fan > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 ++++++++++++++++--- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + > 2 files changed, 17 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 737c5b88235510e3ddb91a28cecbdcdc14854b32..3db7b3e2ac94e16130fc0356f7954ffa1a9dfb33 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -80,6 +80,7 @@ DEFINE_MUTEX(arm_smmu_asid_lock); > static struct arm_smmu_option_prop arm_smmu_options[] = { > { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, > { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"}, > + { ARM_SMMU_OPT_IMX95_BYPASS_SID0, "nxp,imx95-bypass-sid-zero"}, > { 0, NULL}, > }; Aghh, let's not put HW-specific bypass under `arm_smmu_options`. Otherwise, this might become a huge list of SoCs wanting to bypass SIDs. > > @@ -4465,7 +4466,7 @@ static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start, > return devm_ioremap_resource(dev, &res); > } > > -static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) > +static void arm_smmu_install_bypass_ste(struct arm_smmu_device *smmu) > { > struct list_head rmr_list; > struct iommu_resv_region *e; > @@ -4496,6 +4497,18 @@ static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) > } > > iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); > + > + if (smmu->options & ARM_SMMU_OPT_IMX95_BYPASS_SID0) { > + int ret = arm_smmu_init_sid_strtab(smmu, 0); > + > + if (ret) { > + dev_err(smmu->dev, "i.MX95 SID0 bypass failed\n"); > + return; > + } > + > + arm_smmu_make_bypass_ste(smmu, > + arm_smmu_get_step_for_sid(smmu, 0)); > + } > } Umm.. this was specific for rmr not a generic thing. I'd suggest to avoid meddling with the STEs directly for acheiving bypass. Playing with the iommu domain type could be neater. Perhaps, modify the ops->def_domain_type to return an appropriate domain? In general, adding a property/config for bypassing SIDs/devices could potentially cause security concerns if *somehow* a device can spoof an SID. For example, if a PCIe device is bypassed it would be easy for another PCIe endpoint to spoof it's ID. Similarly, certain HW implementations may provide the option to programmable SIDs, for example, a HW register to set SIDs, which if compromised can spoof other SIDs. Although, I'd like to see what the others think about this. > > static void arm_smmu_impl_remove(void *data) > @@ -4614,8 +4627,8 @@ static int arm_smmu_device_probe(struct platform_device *pdev) > /* Record our private device structure */ > platform_set_drvdata(pdev, smmu); > > - /* Check for RMRs and install bypass STEs if any */ > - arm_smmu_rmr_install_bypass_ste(smmu); > + /* Install bypass STEs if any */ > + arm_smmu_install_bypass_ste(smmu); > > /* Reset the device */ > ret = arm_smmu_device_reset(smmu); > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 1e9952ca989f87957197f4d4b400f9d74bb685ac..06481b923284776e7dc4f3301e5cbe8ab7869a9c 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -733,6 +733,7 @@ struct arm_smmu_device { > #define ARM_SMMU_OPT_MSIPOLL (1 << 2) > #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) > #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) > +#define ARM_SMMU_OPT_IMX95_BYPASS_SID0 (1 << 5) > u32 options; > > struct arm_smmu_cmdq cmdq; > > -- > 2.37.1 > > Thanks, Pranjal