From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94747CF11CD for ; Thu, 10 Oct 2024 11:01:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To: Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DgIXQEVq718J0AOS+gfk9iSxH9PGiu+sEAi6yXSQAkA=; b=z+oFDLu8KKKdh0H9qGx3T2RtHG 4fYA8I49VLPobMULzOchYGLzTxlRqG891k3YxIXTYCzgJ7bGG1nocmRV0WfkgZKfmRa1fwaucBODG EF2S3FZ4oJ9nQTKDB4ywnkgs+VVbgXU8IpQUUOgPA9FJZdwVsttYOGnWJpIxtoD+2/3K88rWxzRL2 x7ooqS2d22vzZg/IeQ3qeURTc4rgO2NsdQ/4VvHUtKysIp+9GnDXSHSsAxLdDSTWBVo1i+s9hLeiJ qXZ7Eh5XsTyqwWliT9azl6l87Mil68I+ho8DzkUlapaVqVWfhbX+WfqEsyxzJdRKYRsQbFNKT47yP zDVnb8mA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syqv1-0000000CU98-2OE8; Thu, 10 Oct 2024 11:01:19 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syqsY-0000000CTrP-3FwS for linux-arm-kernel@lists.infradead.org; Thu, 10 Oct 2024 10:58:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57F1B497; Thu, 10 Oct 2024 03:59:15 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8BEB93F58B; Thu, 10 Oct 2024 03:58:43 -0700 (PDT) Date: Thu, 10 Oct 2024 11:58:40 +0100 From: Mark Rutland To: Andrii Nakryiko Cc: Liao Chang , will@kernel.org, catalin.marinas@arm.com, ast@kernel.org, puranjay@kernel.org, andrii@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org, bpf@vger.kernel.org Subject: Re: [PATCH v2] arm64: insn: Simulate nop instruction for better uprobe performance Message-ID: References: <20240909071114.1150053-1-liaochang1@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241010_035847_215806_4491EC4C X-CRM114-Status: GOOD ( 25.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Andrii, On Wed, Oct 09, 2024 at 04:54:25PM -0700, Andrii Nakryiko wrote: > On Mon, Sep 9, 2024 at 12:21 AM Liao Chang wrote: > I'm curious what's the status of this patch? It received no comments > so far in the last month. Can someone on the ARM64 side of things > please take a look? (or maybe it was applied to some tree and there > was just no notification?) > > This is a very useful performance optimization for uprobe tracing on > ARM64, so would be nice to get it in during current release cycle. > Thank you! Sorry, I got busy chasing up a bunch of bugs and hadn't gotten round to this yet. I've replied with a couple of minor comments and an ack, and I reckon we can queue this up this cycle. Usually this sort of thing starts to get queued around -rc3. Mark. > > > diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h > > index 8c0a36f72d6f..dd530d5c3d67 100644 > > --- a/arch/arm64/include/asm/insn.h > > +++ b/arch/arm64/include/asm/insn.h > > @@ -549,6 +549,12 @@ static __always_inline bool aarch64_insn_uses_literal(u32 insn) > > aarch64_insn_is_prfm_lit(insn); > > } > > > > +static __always_inline bool aarch64_insn_is_nop(u32 insn) > > +{ > > + return aarch64_insn_is_hint(insn) && > > + ((insn & 0xFE0) == AARCH64_INSN_HINT_NOP); > > +} > > + > > enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); > > u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); > > u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, > > diff --git a/arch/arm64/kernel/probes/decode-insn.c b/arch/arm64/kernel/probes/decode-insn.c > > index 968d5fffe233..be54539e309e 100644 > > --- a/arch/arm64/kernel/probes/decode-insn.c > > +++ b/arch/arm64/kernel/probes/decode-insn.c > > @@ -75,6 +75,15 @@ static bool __kprobes aarch64_insn_is_steppable(u32 insn) > > enum probe_insn __kprobes > > arm_probe_decode_insn(probe_opcode_t insn, struct arch_probe_insn *api) > > { > > + /* > > + * While 'nop' instruction can execute in the out-of-line slot, > > + * simulating them in breakpoint handling offers better performance. > > + */ > > + if (aarch64_insn_is_nop(insn)) { > > + api->handler = simulate_nop; > > + return INSN_GOOD_NO_SLOT; > > + } > > + > > /* > > * Instructions reading or modifying the PC won't work from the XOL > > * slot. > > diff --git a/arch/arm64/kernel/probes/simulate-insn.c b/arch/arm64/kernel/probes/simulate-insn.c > > index 22d0b3252476..5e4f887a074c 100644 > > --- a/arch/arm64/kernel/probes/simulate-insn.c > > +++ b/arch/arm64/kernel/probes/simulate-insn.c > > @@ -200,3 +200,14 @@ simulate_ldrsw_literal(u32 opcode, long addr, struct pt_regs *regs) > > > > instruction_pointer_set(regs, instruction_pointer(regs) + 4); > > } > > + > > +void __kprobes > > +simulate_nop(u32 opcode, long addr, struct pt_regs *regs) > > +{ > > + /* > > + * Compared to instruction_pointer_set(), it offers better > > + * compatibility with single-stepping and execution in target > > + * guarded memory. > > + */ > > + arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); > > +} > > diff --git a/arch/arm64/kernel/probes/simulate-insn.h b/arch/arm64/kernel/probes/simulate-insn.h > > index e065dc92218e..efb2803ec943 100644 > > --- a/arch/arm64/kernel/probes/simulate-insn.h > > +++ b/arch/arm64/kernel/probes/simulate-insn.h > > @@ -16,5 +16,6 @@ void simulate_cbz_cbnz(u32 opcode, long addr, struct pt_regs *regs); > > void simulate_tbz_tbnz(u32 opcode, long addr, struct pt_regs *regs); > > void simulate_ldr_literal(u32 opcode, long addr, struct pt_regs *regs); > > void simulate_ldrsw_literal(u32 opcode, long addr, struct pt_regs *regs); > > +void simulate_nop(u32 opcode, long addr, struct pt_regs *regs); > > > > #endif /* _ARM_KERNEL_KPROBES_SIMULATE_INSN_H */ > > -- > > 2.34.1 > >