Re: [PATCH v2 08/14] clk: rp1: Add support for clocks provided by RP1

Andrea della Porta
2024-11-14T15:42:36Z

Hi Stephen,

On 15:08 Wed 09 Oct , Stephen Boyd wrote:
> Quoting Andrea della Porta (2024-10-07 05:39:51)
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 299bc678ed1b..537019987f0c 100644

Here's below the kind response from RaspberryPi guys...
...

> > + clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD);
> > + clockman_write(clockman, data->fbdiv_int_reg, fbdiv_int);
> > + clockman_write(clockman, data->fbdiv_frac_reg, fbdiv_frac);
> > + spin_unlock(&clockman->regs_lock);
> > +
> > + /* Check that reference frequency is no greater than VCO / 16. */
>
> Why is '16' special?

16 is a hardware requirement.
The lowest feedback divisor in the PLL is 16, so the minimum output
frequency is ref_freq * 16.

...

> > +static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw,
> > + unsigned long parent_rate)
> > +{
> > + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);
> > + struct rp1_clockman *clockman = pll_core->clockman;
> > + const struct rp1_pll_core_data *data = pll_core->data;
> > + u32 fbdiv_int, fbdiv_frac;
> > + unsigned long calc_rate;
> > +
> > + fbdiv_int = clockman_read(clockman, data->fbdiv_int_reg);
> > + fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg);
> > + calc_rate =
> > + ((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24;
>
> Where does '24' come from? Can you simplify this line somehow? Maybe
> break it up into multiple lines?

The dividers have an 8 bit integer and (optional) 24 bit fractional
part to the divider value.
The two parts are split across two registers (int_reg and frac_reg),
with the value stored in the bottom bits of both.

...

> > +static int rp1_clock_determine_rate(struct clk_hw *hw,
> > + struct clk_rate_request *req)
> > +{
> > + struct clk_hw *parent, *best_parent = NULL;
> > + unsigned long best_rate = 0;
> > + unsigned long best_prate = 0;
> > + unsigned long best_rate_diff = ULONG_MAX;
> > + unsigned long prate, calc_rate;
> > + size_t i;
> > +
> > + /*
> > + * If the NO_REPARENT flag is set, try to use existing parent.
> > + */
> > + if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) {
>
> Is this flag ever set?

In future patches more clocks will be added (namely DPI, DSI (x2) and VEC).
All have the CLK_SET_RATE_NO_REPARENT flag set.
As those peripherals are sensitive to the accuracy of the clocks, the intent
is that the driver will have set the parent, and it isn't expected to change.

...

> > + divider->div.reg = clockman->regs + divider_data->ctrl_reg;
> > + divider->div.shift = PLL_SEC_DIV_SHIFT;
> > + divider->div.width = PLL_SEC_DIV_WIDTH;
> > + divider->div.flags = CLK_DIVIDER_ROUND_CLOSEST;
> > + divider->div.flags |= CLK_IS_CRITICAL;
>
> Is everything critical? The usage of this flag and CLK_IGNORE_UNUSED is
> suspicious and likely working around some problems elsewhere.

the next patchset revision will drop as many of those CRITICAL flags as possible,
and all of the IGNORE_UNUSED flags. That was legacy code needed on bcm-clk2835
since some clocks were enabled by the firmware, and therefore disabling them
had the potential for locking the firmware up. This does no longer apply to RP1.

...

Many thanks,
Andrea