From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C06C8D3C904 for ; Sat, 19 Oct 2024 08:48:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To: Content-Type:MIME-Version:References:Message-ID:Subject:To:Date:From:Reply-To :Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=goIM8l9m337Jc/qmGgmMN6cGaQgYnCJzJED4V8yFMUM=; b=NR2zmADkfoKQd4Ri0kDrZCuNam 8PnezbiWz37oswerD/eAzTVAw7Q1gQCADBnyA5+FbI7TNCQ3O4H0SrgYsoeZmLQdKFQYK0OkcrHqt qtDEMg9Nq/547z++6t1VSHH5VTPPhssEm6yXRqDFVF7Y1xzVWzHf68M4RWK+xX5ZLSjguZrflpiUm gAW0FPqgp4lJkPp0+qROZxh8tmJxRiaV9LLXiEUKPHMp313+aYha0FYI0D5RUW8cQr2RvtAMtJaEJ I9D+48SdJl6cKPGJPdDKwzvk8vyXRtgXTBA3iJV0IhjhJKwHB+4COnOYEOvDbLZzpJLByk4rBJGJw hbj7aCvg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t2589-00000002s9n-0E2N; Sat, 19 Oct 2024 08:48:13 +0000 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t256e-00000002rgS-1ONq for linux-arm-kernel@lists.infradead.org; Sat, 19 Oct 2024 08:46:42 +0000 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-a9a1b71d7ffso409462266b.1 for ; Sat, 19 Oct 2024 01:46:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1729327598; x=1729932398; darn=lists.infradead.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:date:from:from:to:cc:subject:date:message-id:reply-to; bh=goIM8l9m337Jc/qmGgmMN6cGaQgYnCJzJED4V8yFMUM=; b=RSFIRw2vXns1/zHdggAVV4NgAgdotsafU2DKxHoMZ/nkOgXDi4lc7ujhkdfIu10XV6 oBX6K/cVE9VYNK8sgn6XivcXV48IU3RNznMC0tkvlI1rWatqd0ub7XJCSKYMbDiFgP/K c+wpUnnNvZ5WzogwLToWI3F0lddkWVY36vv0dIM+hpkDlhxMzDoGsXMudSf7WiRuzkq4 19pca+Bec6A7fkHf+wrhs21WxHE0y78YMfgcL88u6pwxjElC56p/LnzPCb2pokYTcp9g xFS+WC1Tq0iBkQBMQxWBoELM3VdmT4KqBkgBceKL+0Foc6NsIrM0xYqHPnR61w8HCv/6 wpyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729327598; x=1729932398; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:date:from:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=goIM8l9m337Jc/qmGgmMN6cGaQgYnCJzJED4V8yFMUM=; b=LEQ/nN7zG0TglWNR3GL0J/Ca5TKOF2uZNgbKM3ICTMPVCrhiO1R26ABzpMU7bjSbtb 5hqRuHelsYnpX47uG6kdfCnFNhwVkLAGJTb9ovMqmgfoLDZYItiuj7mTjmkrJtqXkvK6 5pkX3KEEXSL2+wK2NYBVmdfP5UgRC4ifZcWkiUaG0iH3KDhLe9VgpG0fDalqf6n/EF7j pbiTq5YNfn9egL0F08VNgwtYpRbWapXtxEmVMPcMG2jSKFR/ljLuFZSifVA+HEsqinWI jtlHnbz4hVdGDyGzdIVpFmOMEnpkX49gnxRSy1BJoCvQKMV5fFPkforn5VUKPeLR9HVx plAw== X-Forwarded-Encrypted: i=1; AJvYcCVEENcz7DGc4+YuSKKgme5F+ZqGqzIM2nBcQ2XiRzQtoH+UREpUtz//tJFJMPQthdm7VSU+cGSucQS57S9l8i1t@lists.infradead.org X-Gm-Message-State: AOJu0Yzy2QXQt1FUPRGZL+OZXNzOH38/xwXA0BMHOwS18PPddMH62Z/S qYq5f/RfdFYjCU4FmUDiQhO/mGIMJmLUGTl7eCR9vvz6KiFY3CL9iPAwiorTlxw= X-Google-Smtp-Source: AGHT+IE6LjBSGzuHopccP4572hv/igYqTjW1d9uem80OwOh8YbiNrdYIuLnJQku+pZ2TZlmLJ4YdEQ== X-Received: by 2002:a17:907:705:b0:a99:36ab:d843 with SMTP id a640c23a62f3a-a9a69baadbbmr400539166b.38.1729327598506; Sat, 19 Oct 2024 01:46:38 -0700 (PDT) Received: from localhost (host-95-234-228-50.retail.telecomitalia.it. [95.234.228.50]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a68bf7a19sm190806966b.168.2024.10.19.01.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Oct 2024 01:46:37 -0700 (PDT) From: Andrea della Porta X-Google-Original-From: Andrea della Porta Date: Sat, 19 Oct 2024 10:46:58 +0200 To: Bjorn Helgaas Subject: Re: [PATCH 03/11] PCI: of_property: Sanitize 32 bit PCI address parsed from DT Message-ID: References: <20241018222850.GA766393@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241018222850.GA766393@bhelgaas> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241019_014640_415927_D24FE9BC X-CRM114-Status: GOOD ( 45.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Catalin Marinas , Michael Turquette , Claudiu Beznea , Lizhi Hou , Eric Dumazet , Dragan Cvetic , Will Deacon , linux-clk@vger.kernel.org, linux-arch@vger.kernel.org, Rob Herring , Florian Fainelli , Lee Jones , Saravana Kannan , Broadcom internal kernel review list , linux-pci@vger.kernel.org, Jakub Kicinski , Paolo Abeni , Linus Walleij , devicetree@vger.kernel.org, Conor Dooley , Arnd Bergmann , linux-gpio@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, Bjorn Helgaas , Andrea della Porta , linux-arm-kernel@lists.infradead.org, Derek Kiernan , Stephen Boyd , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Stefan Wahren , netdev@vger.kernel.org, Krzysztof Kozlowski , "David S. Miller" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Bjorn, On 17:28 Fri 18 Oct , Bjorn Helgaas wrote: > On Fri, Oct 18, 2024 at 02:41:11PM +0200, Andrea della Porta wrote: > > On 20:08 Mon 07 Oct , Bjorn Helgaas wrote: > > ... > > > > Yes, this is exactly the problem. The pci@0 parent and child > > > addresses in "ranges" are both in the PCI address space. But we > > > start with pdev->resource[N], which is a CPU address. To get the PCI > > > address, we need to apply pci_bus_address(). If the host bridge > > > windows are set up correctly, the window->offset used in > > > pcibios_resource_to_bus() should yield the PCI bus address. > > > > You mean something like this, I think: > > > > @@ -129,7 +129,7 @@ static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs, > > if (of_pci_get_addr_flags(&res[j], &flags)) > > continue; > > > > - val64 = res[j].start; > > + val64 = pci_bus_address(pdev, &res[j] - pdev->resource); > > of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags, > > false); > > if (pci_is_bridge(pdev)) { > > Yes. > > > > I think it should look like this: > > > > > > pci@0: <0x82000000 0x0 0x00000000 0x82000000 0x0 0x00000000 0x0 0x600000>; > > > > indeed, with the above patch applied, the result is exactly as you expected. > > ... > > > > > > But I don't think it works in general because there's no > > > > > requirement that the host bridge address translation be that > > > > > simple. For example, if we have two host bridges, and we want > > > > > each to have 2GB of 32-bit PCI address space starting at 0x0, > > > > > it might look like this: > > > > > > > > > > 0x00000002_00000000 -> PCI 0x00000000 (subtract 0x00000002_00000000) > > > > > 0x00000002_80000000 -> PCI 0x00000000 (subtract 0x00000002_80000000) > > > > > > > > > > In this case simply ignoring the high 32 bits of the CPU > > > > > address isn't the correct translation for the second host > > > > > bridge. I think we should look at each host bridge's > > > > > "ranges", find the difference between its parent and child > > > > > addresses, and apply the same difference to everything below > > > > > that bridge. > > > > > > > > Not sure I've got this scenario straight: can you please provide > > > > the topology and the bit setting (32/64 bit) for those ranges? > > > > Also, is this scenario coming from a real use case or is it > > > > hypothetical? > > > > > > This scenario is purely hypothetical, but it's a legal topology > > > that we should handle correctly. It's two host bridges, with > > > independent PCI hierarchies below them: > > > > > > Host bridge A: [mem 0x2_00000000-0x2_7fffffff window] (bus address 0x00000000-0x7fffffff) > > > Host bridge B: [mem 0x2_80000000-0x2_ffffffff window] (bus address 0x00000000-0x7fffffff) > > > > > > Bridge A has an MMIO aperture at CPU addresses > > > 0x2_00000000-0x2_7fffffff, and when it initiates PCI transactions on > > > its secondary side, the PCI address is CPU_addr - 0x2_00000000. > > > > > > Similarly, bridge B has an MMIO aperture at CPU addresses > > > 0x2_80000000-0x2_ffffffff, and when it initiates PCI transactions on > > > its secondary side, the PCI address is CPU_addr - 0x2_80000000. > > > > > > Both hierarchies use PCI bus addresses in the 0x00000000-0x7fffffff > > > range. In a topology like this, you can't convert a bus address back > > > to a CPU address unless you know which hierarchy it's in. > > > pcibios_bus_to_resource() takes a pci_bus pointer, which tells you > > > which hierarchy (and which host bridge address translation) to use. > > > > Agreed. While I think about how to adjust that specific patch,i > > let's drop it from this patchset since the aforementioned change is > > properly fixing the translation issue. > > OK. I assume you mean to drop the "PCI: of_property: Sanitize 32 bit > PCI address parsed from DT" patch? Or replace it with the > pci_bus_address() addition above? I'm planning to replace that patch with the above mentioned pci_bus_address() addition. However, I think the 32 bit sanitization is still useful to prevent wrongly encoded address to linger around, but I defer it to a subsequent standalone patch, after figuring out the dual bridge scenario that you proposed. > > Bjorn Many thanks, Andrea