From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39167D2CE01 for ; Tue, 22 Oct 2024 16:48:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5u/dcCKIAOr6QbvfsgUi5dh66c3mHuT2Ibiom/3+/Fs=; b=JOGE/CFwBZnkt6w+0znBmuPmJ6 b5Qz7txxuqdxLNvf6XPSdm0pUP5PsGChncMAHhUgqDGyWM9v19tRWInAwEl5RgOPL/WPaVU5I/oyQ 8vtxQcfzx+Fk0Zkl9Les7/71deGufnI0QWzz9TTcMQ4YmIE9ZJTQTrpLdOp6UQ/ivWqrp9go28TDZ BIpj+tfbm3sZoPnPtfTB85EBw3GejQ6Ro0jj55/6YRElp/DkC0hZ7W/tGK3XU2WbZ+mvwq+XKAxb4 wOuMRJ9bOkMufDX30CCZEdy88FHb1h6XRGe3BLZXXfET7Iq3KBrexnqee8IX5rAg+dcm6iNCnUxlY zDIkYtxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t3I2w-0000000BWtm-0isq; Tue, 22 Oct 2024 16:47:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t3HSz-0000000BOPo-0G1w for linux-arm-kernel@lists.infradead.org; Tue, 22 Oct 2024 16:10:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07E99497; Tue, 22 Oct 2024 09:11:10 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CCF923F73B; Tue, 22 Oct 2024 09:10:37 -0700 (PDT) Date: Tue, 22 Oct 2024 17:10:34 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org Subject: Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Message-ID: References: <20241001043602.1116991-1-anshuman.khandual@arm.com> <20241001043602.1116991-3-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241001043602.1116991-3-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241022_091041_209085_975367C8 X-CRM114-Status: GOOD ( 14.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 01, 2024 at 10:06:01AM +0530, Anshuman Khandual wrote: > Fine grained trap control for MDSELR_EL1 register needs to be configured in > HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 > is also present. This adds a new helper __init_el2_fgt2() initializing this > new FEAT_FGT2 based fine grained registers. > > MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and > watchpoint exceptions when kernel enters at EL1, but EL2 is also present. > This updates __init_el2_debug() as required for FEAT_Debugv8p9. > > While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. [...] > + For CPUs with FEAT_Debugv8p9 extension present: > + > + - If the kernel is entered at EL1 and EL2 is present: > + > + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 > + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 > + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 > + > + - If EL3 is present: > + > + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 AFAICT we need TDA==0 this regardless of FEAT_Debugv8p9 (and e.g. we need MDCR_EL3.TPM==0 where FEAT_PMUv3 is implemented), so we should probably check if there's anything else we haven't yet documented in MDCR_EL3. [...] > .Lskip_trace_\@: > + mrs x1, id_aa64dfr0_el1 > + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 > + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 > + b.lt .Lskip_dbg_v8p9_\@ > + > + mov x0, #MDCR_EL2_EBWE > + orr x2, x2, x0 That can be: orr x2, x2, #MDCR_EL2_EBWE Mark.