From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8E3EE68975 for ; Thu, 31 Oct 2024 11:46:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TUeHarXNuUyAu3316kaB1fiLCzjd7oxMbwA/mfb5Ob0=; b=L9Vj71F2PK+dWU9OmxVCZdKRYA TD312OozrjD18gYwjYBQWo4G94fTy0QSnAjqDhA279PTx0KBZ2Fiq8hQc+z8qvUugwrzUJQLTJn6i k4Fv/Tc9TH+RXYGKvCPK/zswkEUd4eyBsQp2jl1c4wMvEyrXqOYGyGZ1AKjzDbIq8LndshQfUKf8Z h8U3DlWtDD4QO2ZIsoHgy57XEOg+9i+6KmiqGel5z5g1VOpjrZMApqORJoYCHWgW+cqseXZNY9mFY Bj0in/jn4H4e8AicaR7CqGGZVnXeb7obdCTMBCAXHS82OblHiadHl/JlkupVl7T119ou/zzdPkh3X J9Nm4ZUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t6TdQ-00000003RPq-3utn; Thu, 31 Oct 2024 11:46:40 +0000 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t6Tbl-00000003R4m-0rPM for linux-arm-kernel@lists.infradead.org; Thu, 31 Oct 2024 11:44:58 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 7CBAEA44130; Thu, 31 Oct 2024 11:43:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 92066C4CEDE; Thu, 31 Oct 2024 11:44:53 +0000 (UTC) Date: Thu, 31 Oct 2024 11:44:51 +0000 From: Catalin Marinas To: Joey Gouly Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, anshuman.khandual@arm.com, gshan@redhat.com, james.morse@arm.com, shameerali.kolothum.thodi@huawei.com, Marc Zyngier , Oliver Upton , Suzuki K Poulose , Zenghui Yu , Jing Zhang , Will Deacon Subject: Re: [PATCH v6 3/7] arm64: cpufeature: discover CPU support for MPAM Message-ID: References: <20241030160317.2528209-1-joey.gouly@arm.com> <20241030160317.2528209-4-joey.gouly@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241030160317.2528209-4-joey.gouly@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241031_044457_325405_5EB8B306 X-CRM114-Status: GOOD ( 17.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 30, 2024 at 04:03:13PM +0000, Joey Gouly wrote: > From: James Morse > > ARMv8.4 adds support for 'Memory Partitioning And Monitoring' (MPAM) > which describes an interface to cache and bandwidth controls wherever > they appear in the system. > > Add support to detect MPAM. Like SVE, MPAM has an extra id register that > describes some more properties, including the virtualisation support, > which is optional. Detect this separately so we can detect > mismatched/insane systems, but still use MPAM on the host even if the > virtualisation support is missing. > > MPAM needs enabling at the highest implemented exception level, otherwise > the register accesses trap. The 'enabled' flag is accessible to lower > exception levels, but its in a register that traps when MPAM isn't enabled. > The cpufeature 'matches' hook is extended to test this on one of the > CPUs, so that firmware can emulate MPAM as disabled if it is reserved > for use by secure world. > > Secondary CPUs that appear late could trip cpufeature's 'lower safe' > behaviour after the MPAM properties have been advertised to user-space. > Add a verify call to ensure late secondaries match the existing CPUs. > > (If you have a boot failure that bisects here its likely your CPUs > advertise MPAM in the id registers, but firmware failed to either enable > or MPAM, or emulate the trap as if it were disabled) > > Signed-off-by: James Morse > Signed-off-by: Joey Gouly > Reviewed-by: Gavin Shan > Tested-by: Shameer Kolothum Acked-by: Catalin Marinas