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Tue, 05 Nov 2024 02:00:52 -0800 (PST) Received: from linaro.org ([82.76.168.176]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4327d5bf4e7sm181024905e9.15.2024.11.05.02.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Nov 2024 02:00:51 -0800 (PST) Date: Tue, 5 Nov 2024 12:00:50 +0200 From: Abel Vesa To: "Peng Fan (OSS)" Cc: Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Aisheng Dong , linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan , Jacky Bai Subject: Re: [PATCH v3 3/5] clk: imx: fracn-gppll: fix pll power up Message-ID: References: <20241027-imx-clk-v1-v3-0-89152574d1d7@nxp.com> <20241027-imx-clk-v1-v3-3-89152574d1d7@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241027-imx-clk-v1-v3-3-89152574d1d7@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241105_020054_307876_42100C93 X-CRM114-Status: GOOD ( 28.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24-10-27 20:00:09, Peng Fan (OSS) wrote: > From: Peng Fan > > To i.MX93 which features dual Cortex-A55 cores and DSU, when using > writel_relaxed to write value to PLL registers, the value might be > buffered. To make sure the value has been written into the hardware, > using readl to read back the register could achieve the goal. > > current PLL power up flow can be simplified as below: > 1. writel_relaxed to set the PLL POWERUP bit; > 2. readl_poll_timeout to check the PLL lock bit: > a). timeout = ktime_add_us(ktime_get(), timeout_us); > b). readl the pll the lock reg; > c). check if the pll lock bit ready > d). check if timeout > > But in some corner cases, both the write in step 1 and read in > step 2 will be blocked by other bus transaction in the SoC for a > long time, saying the value into real hardware is just before step b). > That means the timeout counting has begins for quite sometime since > step a), but value still not written into real hardware until bus > released just at a point before step b). > > Then there maybe chances that the pll lock bit is not ready > when readl done but the timeout happens. readl_poll_timeout will > err return due to timeout. To avoid such unexpected failure, > read back the reg to make sure the write has been done in HW > reg. > > So use readl after writel_relaxed to fix the issue. > > Since we are here, to avoid udelay to run before writel_relaxed, use > readl before udelay. > > Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") > Co-developed-by: Jacky Bai > Signed-off-by: Jacky Bai > Signed-off-by: Peng Fan Reviewed-by: Abel Vesa > --- > drivers/clk/imx/clk-fracn-gppll.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c > index 4749c3e0b7051cf53876664808aa28742f6861f7..85771afd4698ae6a0d8a7e82193301e187049255 100644 > --- a/drivers/clk/imx/clk-fracn-gppll.c > +++ b/drivers/clk/imx/clk-fracn-gppll.c > @@ -254,9 +254,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, > pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | > FIELD_PREP(PLL_MFI_MASK, rate->mfi); > writel_relaxed(pll_div, pll->base + PLL_DIV); > + readl(pll->base + PLL_DIV); > if (pll->flags & CLK_FRACN_GPPLL_FRACN) { > writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR); > writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR); > + readl(pll->base + PLL_NUMERATOR); > } > > /* Wait for 5us according to fracn mode pll doc */ > @@ -265,6 +267,7 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, > /* Enable Powerup */ > tmp |= POWERUP_MASK; > writel_relaxed(tmp, pll->base + PLL_CTRL); > + readl(pll->base + PLL_CTRL); > > /* Wait Lock */ > ret = clk_fracn_gppll_wait_lock(pll); > @@ -302,6 +305,7 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw) > > val |= POWERUP_MASK; > writel_relaxed(val, pll->base + PLL_CTRL); > + readl(pll->base + PLL_CTRL); > > ret = clk_fracn_gppll_wait_lock(pll); > if (ret) > > -- > 2.37.1 >