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From: Oliver Upton To: Raghavendra Rao Ananta Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH] KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status Message-ID: References: <20241119205841.268247-1-rananta@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241119205841.268247-1-rananta@google.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241119_133528_626213_5E326E25 X-CRM114-Status: GOOD ( 11.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Raghu, Thanks for finding this! On Tue, Nov 19, 2024 at 08:58:41PM +0000, Raghavendra Rao Ananta wrote: > kvm_pmu_overflow_status() currently checks if the PMCs are enabled for > evaluating the PMU overflow condition. However, ARM ARM D13.1.1 states > that a global enable control (PMCR.E), PMOVSSET, and PMINTENSET > are sufficent to consider that the overflow condition is met. Hence, > ignore the check for PMCNTENSET. It's more than sufficient, evaluating E, PMOVSSET, and PMINTENSET is the *only* correct implementation of the architecture. Also, ARM ARM section numbering is subject to change between revisions, so it's always best to use a fully-qualified citation, like 'DDI0487K D13.1.1'. So I may rewrite this as: DDI0487K D13.1.1 describes the PMU overflow condition, which evaluates to true if any counter's global enable (PMCR_EL0.E), overflow flag (PMOVSSET_EL0[n]), and interrupt enable (PMINTENSET_EL1[n]) are all 1. Of note, this does not require a counter to be enabled (i.e. PMCNTENSET_EL0[n] = 1) to generate an overflow. Align kvm_pmu_overflow_status() with the reality of the architecture and stop using PMCNTENSET_EL0 as part of the overflow condition. We've got yet another bug lurking here as of 6.13, since the hypervisor range of counters isn't observing the correct global enable (MDCR_EL2.HPME). Let me fiddle with this and send out a combined set of fixes. > The bug was discovered while running the SBSA PMU test, which only sets > PMCR.E, PMOVSSET<0>, PMINTENSET<0>, and expects an overflow interrupt. > We should be sending this to stable too. Cc: stable@vger.kernel.org Fixes: 76d883c4e640 ("arm64: KVM: Add access handler for PMOVSSET and PMOVSCLR register") -- Thanks, Oliver