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[34.79.100.158]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab78918sm61906695e9.17.2024.11.15.11.18.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 11:18:40 -0800 (PST) Date: Fri, 15 Nov 2024 19:18:36 +0000 From: Mostafa Saleh To: Robin Murphy Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, joro@8bytes.org, Daniel Mentz Subject: Re: [PATCH] drivers/io-pgtable-arm: Fix stage concatenation with 16K Message-ID: References: <20241115172235.1493328-1-smostafa@google.com> <888e6542-2aa4-43f1-b31e-79432c1ad199@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <888e6542-2aa4-43f1-b31e-79432c1ad199@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241115_111844_690674_54A8CA87 X-CRM114-Status: GOOD ( 32.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Robin, On Fri, Nov 15, 2024 at 06:29:20PM +0000, Robin Murphy wrote: > On 2024-11-15 5:22 pm, Mostafa Saleh wrote: > > According to the Arm spec DDI0487 K.a, in: > > "Table D8-9 Implications of the effective minimum T0SZ value on the > > initial stage 2 lookup level" > > > > Some combinations of granule and input size with stage-2 would > > require to use initial lookup levels that can only be achieved > > with concatenated PGDs. > > > > There was one missing case in the current implementation for 16K, > > which is 40-bits. > > > > Cc: Daniel Mentz > > > > Signed-off-by: Mostafa Saleh > > --- > > drivers/iommu/io-pgtable-arm.c | 14 +++++++++++--- > > 1 file changed, 11 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c > > index 0e67f1721a3d..9a57874a5cb8 100644 > > --- a/drivers/iommu/io-pgtable-arm.c > > +++ b/drivers/iommu/io-pgtable-arm.c > > @@ -1044,10 +1044,18 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) > > return NULL; > > /* > > - * Concatenate PGDs at level 1 if possible in order to reduce > > - * the depth of the stage-2 walk. > > + * Some cases where concatenation is mandatory after de-ciphering RSRKBC > > + * in the Arm DDI0487 (K.a): > > + * - 40 bits with 4K: use 2 table at level 1 instead of level 0 > > + * - 40 bits with 16K: use 16 tables at level 2 instead of level 1 > > + * - 42 bits with 4K: use 8 tabels at level 1 instead of level 0 > > + * - 48 bits with 16K: use 2 tabels at level 1 instead of level 0 > > This confused me, since per R_DXBSH, that last one is the only one which is > actually mandatory in general; the others may be valid per R_PZFHQ and > R_FBHPY. The additional R_SRKBC constraints come from the PA size, not the > choice of T0SZ (and thus ultimately start_level) itself, so although I guess > this probably works out true in practice based on how the SMMU drivers > happen to behave today, it's none too obvious why. Ah, you are right, I got a bit confused, it's not actually about the input size, but the fact that the SMMUv3 driver uses IAS = OAS for stage-2. And constraint R_SRKBC is about the OAS size. So in case we change that IAS = OAS for stage-2, we could end up using concatenation when it's not mandatory. I don't think that's a bad thing (I was actually thinking of changing the code to always use concatenation if possible) But, I can re-write the code in terms of OAS + granule instead so it's more robust incase we change the stage-2 config in the future. Thanks, Mostafa > > Thanks, > Robin. > > > + * Looking at the possible valid input size, that concludes to always > > + * use level 1 with concatentation if possible or at level 2 only > > + * with 16K. > > */ > > - if (data->start_level == 0) { > > + if ((data->start_level == 0) || > > + ((data->start_level == 1) && (ARM_LPAE_GRANULE(data) == SZ_16K))) { > > unsigned long pgd_pages; > > pgd_pages = ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte); >