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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tiINX-00000008d9R-23pC; Wed, 12 Feb 2025 19:26:35 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tiIM5-00000008crn-15kf; Wed, 12 Feb 2025 19:25:06 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 08D945C6194; Wed, 12 Feb 2025 19:24:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7737FC4CEDF; Wed, 12 Feb 2025 19:24:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739388304; bh=7sesecLH7TnirzeBcMYhfkDs4c2KfL3v0QPmpCbmrjE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=fXXOzCdXve+Cj0IcPQfCSkT54RQbKorXd/SFMTBClDoXtj0zTZEi8L2oDTOtqDvhA vRZsUw6on+dtKrngKRf0NyZV6L1UClNLFczOhoFaCLtqS8woQYrN+tZhUVpjP49Ijc S0GYPyrL6o+0s1CAxQaWwJlWqj56Q9wI3QKPUxpUgAnkfUZVwzHrucs8vURKRxUVkH kPFfxDwiMbeeDRSZ3YSfI8yS5t8XDyzdOZ1DuLC5UQZi7hyA0ZM3WglEBQUayfNqed YZrGjmAm399SwRplMlsaqGUQY4BC4ztkPJxKCCS6657WPNaG+dxp2MMX5HU7mf1BYh kMQhZzdwi8G2A== Message-ID: Date: Wed, 12 Feb 2025 20:24:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files To: Alexander Sverdlin , Inochi Amaoto , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Chao Wei References: <20250210220951.1248533-1-alexander.sverdlin@gmail.com> <20250210220951.1248533-2-alexander.sverdlin@gmail.com> <708cdc497b8474609989395dbf8a0898037a22de.camel@gmail.com> <33654180-5488-4601-9103-8e4218c4a198@kernel.org> <26ddcdaadd777f170dbab51ab840c899f0edde24.camel@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250212_112505_418646_1C0719C3 X-CRM114-Status: GOOD ( 19.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/02/2025 18:44, Alexander Sverdlin wrote: > Hi > > On Wed, 2025-02-12 at 17:46 +0100, Krzysztof Kozlowski wrote: >>>>> Make the peripheral device tree re-usable on ARM64 platform by moving CPU >>>>> core and interrupt controllers' parts into the respective per-SoC .dtsi >>>>> files. >>>>> >>>>> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering >>>>> into "plic" interrupt-controller numbering. >>>>> >>>>> Have a nice refactoring side-effect that "plic" and "clint" "compatible" >>>>> property is not specified outside of the corresponding device itself. >>>>> >>>>> Signed-off-by: Alexander Sverdlin >>>>> --- >>>>> Changelog: >>>>> v2: >>>>> - instead of carving out peripherals' part, carve out ARCH-specifics (CPU >>>>> core, interrupt controllers) and spread them among 3 SoC .dtsi files which >>>>> included cv18xx.dtsi; >>>>> - define a label for the "soc" node and use it in the newly introduced DTs; >>>>> >>>>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi    | 64 ++++++++++++--- >>>>>  arch/riscv/boot/dts/sophgo/cv1812h.dtsi    | 64 ++++++++++++--- >>>>>  arch/riscv/boot/dts/sophgo/cv181x.dtsi     |  2 +- >>>>>  arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++ >>>>>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi     | 91 ++++++---------------- >>>>>  arch/riscv/boot/dts/sophgo/sg2002.dtsi     | 64 ++++++++++++--- >>>>>  6 files changed, 240 insertions(+), 102 deletions(-) >>>>>  create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi >>>>> >>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>>> index aa1f5df100f0..eef2884b36f9 100644 >>>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi >>>>> @@ -3,6 +3,8 @@ >>>>>   * Copyright (C) 2023 Jisheng Zhang >>>>>   */ >>>>>   >>>>> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) >>>>> + >>>>>  #include >>>>>  #include "cv18xx.dtsi" >>>>>   >>>>> @@ -14,22 +16,62 @@ memory@80000000 { >>>>>   reg = <0x80000000 0x4000000>; >>>>>   }; >>>>>   >>>> >>>>> - soc { >>>>> - pinctrl: pinctrl@3001000 { >>>>> - compatible = "sophgo,cv1800b-pinctrl"; >>>>> - reg = <0x03001000 0x1000>, >>>>> -       <0x05027000 0x1000>; >>>>> - reg-names = "sys", "rtc"; >>>> >>>> >>>>> + cpus: cpus { >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + timebase-frequency = <25000000>; >>>>> + >>>>> + cpu0: cpu@0 { >>>>> + compatible = "thead,c906", "riscv"; >>>>> + device_type = "cpu"; >>>>> + reg = <0>; >>>>> + d-cache-block-size = <64>; >>>>> + d-cache-sets = <512>; >>>>> + d-cache-size = <65536>; >>>>> + i-cache-block-size = <64>; >>>>> + i-cache-sets = <128>; >>>>> + i-cache-size = <32768>; >>>>> + mmu-type = "riscv,sv39"; >>>>> + riscv,isa = "rv64imafdc"; >>>>> + riscv,isa-base = "rv64i"; >>>>> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", >>>>> +        "zifencei", "zihpm"; >>>>> + >>>>> + cpu0_intc: interrupt-controller { >>>>> + compatible = "riscv,cpu-intc"; >>>>> + interrupt-controller; >>>>> + #interrupt-cells = <1>; >>>>> + }; >>>>>   }; >>>>>   }; >>>>>  }; >>>> >>>> Make all soc definition include the common cpu file. >>>> Not just copy it. >>> >>> I was acting according to Krzysztof's suggestion: >>> https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/ >>> >>> Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt >>> controllers into it. Would it make sense? >> >> >> I don't understand the original suggestion. > > This is the snippet in question: > > ---[ cut ]--- > #define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > / { > cpus: cpus { > #address-cells = <1>; > #size-cells = <0>; > timebase-frequency = <25000000>; > > cpu0: cpu@0 { > compatible = "thead,c906", "riscv"; > device_type = "cpu"; > reg = <0>; > d-cache-block-size = <64>; > d-cache-sets = <512>; > d-cache-size = <65536>; > i-cache-block-size = <64>; > i-cache-sets = <128>; > i-cache-size = <32768>; > mmu-type = "riscv,sv39"; > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > "zifencei", "zihpm"; > > cpu0_intc: interrupt-controller { > compatible = "riscv,cpu-intc"; > interrupt-controller; > #interrupt-cells = <1>; > }; > }; > }; > }; > > &soc { > interrupt-parent = <&plic>; > dma-noncoherent; > > plic: interrupt-controller@70000000 { > reg = <0x70000000 0x4000000>; > interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > interrupt-controller; > #address-cells = <0>; > #interrupt-cells = <2>; > riscv,ndev = <101>; > }; > > clint: timer@74000000 { > reg = <0x74000000 0x10000>; > interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; > }; > }; > ---[ cut ]--- > > Inochi's proposal is to put it into separate cv18xx-cpu-intc.dtsi and > include the latter in 3 other SoC-specific .dtsis. In v2 I've just > duplicated the above snippet 3 times (refer to diffstat above). > > What are your thoughts? In Renesas everything is duplicated, I believe. > Sophgo outsources much smaller snippets into .dtsi (refer to cv181x.dtsi). If it represents some shared design/part, then it feels good. Best regards, Krzysztof