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Fri, 15 Feb 2019 21:37:19 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Fri, 15 Feb 2019 21:37:19 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Fri, 15 Feb 2019 21:37:19 -0600 Received: from [172.22.218.182] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1G3bDcn024612; Fri, 15 Feb 2019 21:37:14 -0600 Subject: Re: [PATCH v5 00/10] Add support for TISCI irqchip drivers To: , Tony Lindgren , Nishanth Menon , Santosh Shilimkar , Rob Herring , , References: <20190212074237.2875-1-lokeshvutla@ti.com> From: Lokesh Vutla Message-ID: Date: Sat, 16 Feb 2019 09:07:12 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: <20190212074237.2875-1-lokeshvutla@ti.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190215_193736_042123_9393637B X-CRM114-Status: GOOD ( 18.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Device Tree Mailing List , Peter Ujfalusi , Sekhar Nori , linux-kernel@vger.kernel.org, Tero Kristo , Linux ARM Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 2/12/2019 1:12 PM, Lokesh Vutla wrote: > TI AM65x SoC based on K3 architecture introduced support for Events > which are message based interrupts with minimal latency. These events > are not compatible with regular interrupts and are valid only through > an event transport lane. An Interrupt Aggregator(INTA) is introduced > to convert these events to interrupts. INTA can also group 64 events > into a single interrupt. Now the SoC has many peripherals and a large > number of event sources (time sync or DMA), the use of events is > completely dependent on a user's specific application, which drives a > need for maximum flexibility in which event sources are used in the > system. It is also completely up to software control as to how the > events are serviced. > > Because of the huge flexibility there are certain standard peripherals > (like GPIO etc)where all interrupts cannot be directly corrected to host > interrupt controller. For this purpose, Interrupt Router(INTR) is > introduced in the SoC. INTR just does a classic interrupt redirection. > > So the SoC has 3 types of interrupt controllers: > - GIC500 > - Interrupt Router > - Interrupt Aggregator > > Below is a diagrammatic view of how SoC integration of these interrupt > controllers:(https://pastebin.ubuntu.com/p/9ngV3jdGj2/) > > Device Index-x Device Index-y > | | > | | > .... > \ / > \ / > \ (global events) / > +---------------------------+ +---------+ > | | | | > | INTA | | GPIO | > | | | | > +---------------------------+ +---------+ > | (vint) | > | | > \|/ | > +---------------------------+ | > | |<-------+ > | INTR | > | | > +---------------------------+ > | > | > \|/ (gic irq) > +---------------------------+ > | | > | GIC | > | | > +---------------------------+ > > While at it, TISCI abstracts the handling of all above IRQ routes where > interrupt sources are not directly connected to host interrupt controller. > That would be configuration of Interrupt Aggregator and Interrupt Router. > > This series adds support for: > - TISCI commands needed for IRQ configuration > - Interrupt Router(INTR) and Interrupt Aggregator(INTA) drivers Sorry to bother you again. Any chance you can take a quick look at the series? Thanks and regards, Lokesh _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel