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Mon, 10 Nov 2025 21:13:20 -0800 From: Nicolin Chen To: , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v5 5/5] pci: Suspend iommu function prior to resetting a device Date: Mon, 10 Nov 2025 21:12:55 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37A:EE_|SA1PR12MB6871:EE_ X-MS-Office365-Filtering-Correlation-Id: 279c5b1d-5a07-4932-4bfa-08de20e10e6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ltn1gNgobxlClyLIZ0DvNvMuqpsc2pi4/eJZrntRrV9/gDurj5coYc5ED+e8?= =?us-ascii?Q?fy9XgKJtZPREwWlpooocvLj8zWOmHNqH+2NLvZv1CL82nVIQkF2Xc3jjU39O?= =?us-ascii?Q?OoeJm72e42helZ6JZmjhoggU1ISzSSl4oFlC5MzsNUXvYo8XKB0I4LzAqjbX?= =?us-ascii?Q?bB3qX+7xAuvMlBXyciXt6WXAE+3pMGrz7zg+Dxu4U6OqqwnLX5Jj4GF/ulnC?= =?us-ascii?Q?hd8Ud/G/6jfAj7cTgoQkmj7q3vLbz+luIzPnd6Qk+Cp7/wiuMyQBX7jIPL9C?= =?us-ascii?Q?a6BJtl/JLwrIPtwCKNozzM5HFZbhE7JmcVqfXpFFxDowSg8nH+5ogjBgH07Y?= =?us-ascii?Q?VgehLVa2N1NEfhfrTRLi8RUoObiqjvDUHMZbCbX/gw+Ns9ymEZrTv9Dxz8hO?= =?us-ascii?Q?mQ1DHvumaGJBQVHuaofePjppoCCF5k9FTaJJonZT8GZAeO9LRotiENNgV8Vh?= =?us-ascii?Q?feinlQWWOpa7BlpXDOo5c/Ow7jVosBxujVJsbzMNPsT0Aoc1HOpGI2PYmd85?= =?us-ascii?Q?VhpQncJjanLVWNBpQOwq87oGOou9lsRoHBt7NxIA6y8kDQwbZA6ZjJky8Fjl?= =?us-ascii?Q?JujNWxGJJzals4BLTofsAdRhuhlb0avzxzK4riBiDKTjUOjxiDJcjKvXQAmD?= =?us-ascii?Q?WUItOplDoAKFe5QRAURUa6V9M2pwpedeWDFMX+QEiP6/FvBAA5d//Zz5TJb6?= =?us-ascii?Q?LeVuOTdVLsL1/BbiNFiVCAtFj3y5zVkanNeBAMVBQUQOzqD8k7nIKVoqxclC?= =?us-ascii?Q?E9Q+2ItGDh99q4EQ+NrGbScfBWFzlFxogCL4QyIl+4Ob1RqrlRrrtHtgcHKL?= =?us-ascii?Q?S+w4VLrqM896PD0kfHPzk7GtMRd+mf+Qbj5CVDS4yS4wmNIWPswSfn788NkH?= =?us-ascii?Q?OcWiHT+GEZ1vPr1btUJNUYW9FR9/Hlynf+Pfj3cW1KlSkyOBwJlKFaHWjJnE?= =?us-ascii?Q?yt3ymLkPmGlcHX10BtiRp/qCGEdcRo9lfxpMkC1SNxVDQ213xki0xnYTVLQb?= =?us-ascii?Q?RB94GECRkrTq6k1nbylzWcUT3psqBr+ErL14zywwpNiPHXlo0nes6k906Cgw?= =?us-ascii?Q?BPsK6yfR1SZf4afB+gXnw9L+rpvSRJcGJEMxIOx5mZ1Sxuap9O3suWRGODpS?= =?us-ascii?Q?Db+Oy2IufinYoOrlwT/SOxx5Z6hNS+2eXzc144ZdHznSdjRRQwBkjPOYp1La?= =?us-ascii?Q?2fCXCv1zznC4T5NaXzlHpyti3OVePI0V0wmkClpMWFwC2eE6D8fX5B53uWVl?= =?us-ascii?Q?Y4KDVClmycSIjBARRf9GBfWH9Jd9SxC3DXCVwwEEeCcEAWJJfgt8x/aa9TIh?= =?us-ascii?Q?TA3w3hiKVeqomlg5ih+1RQfZqNP6LJSB4Oo9AgzZYcXnNsRM2h3EIRgnib6c?= =?us-ascii?Q?PBq53oomwHfUy4N62+HnA/JnfFhCSqo2VW1tyiMqEuMSk5k5AltqGQw26tjb?= =?us-ascii?Q?iwqn8W3P4c/nzOJZU7NQ4Np6N4Ox8T5b6ejc0p+o2pCm2EYB0gXJot4Hegpi?= =?us-ascii?Q?YP4fom4upJGBXOPJdDiUAs7sAsVKGwfsv98CjMf4S3UT0el1AWjvI+8awJ6J?= =?us-ascii?Q?knqzGkhcBJN3yz7c6Rs=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 05:13:31.3237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 279c5b1d-5a07-4932-4bfa-08de20e10e6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6871 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251110_211339_833979_BE2E9650 X-CRM114-Status: GOOD ( 18.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org PCIe permits a device to ignore ATS invalidation TLPs, while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out: e.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The PCIe spec in sec 10.3.1 IMPLEMENTATION NOTE recommends to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. Now iommu_dev_reset_prepare/done() helpers are introduced for this matter. Use them in all the existing reset functions, which will attach the device to an IOMMU_DOMAIN_BLOCKED during a reset, so as to allow IOMMU driver to: - invoke pci_disable_ats() and pci_enable_ats(), if necessary - wait for all ATS invalidations to complete - stop issuing new ATS invalidations - fence any incoming ATS queries Signed-off-by: Nicolin Chen --- drivers/pci/pci.h | 2 ++ drivers/pci/pci-acpi.c | 12 ++++++-- drivers/pci/pci.c | 68 ++++++++++++++++++++++++++++++++++++++---- drivers/pci/quirks.c | 18 ++++++++++- 4 files changed, 92 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4492b809094b5..a29286dfd870c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -198,6 +198,8 @@ void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); int __pci_reset_bus(struct pci_bus *bus); +int pci_reset_iommu_prepare(struct pci_dev *dev); +void pci_reset_iommu_done(struct pci_dev *dev); struct pci_cap_saved_data { u16 cap_nr; diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9369377725fa0..60d29b183f2c2 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -971,6 +971,7 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) { acpi_handle handle = ACPI_HANDLE(&dev->dev); + int ret = 0; if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; @@ -978,12 +979,19 @@ int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) if (probe) return 0; + ret = pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { pci_warn(dev, "ACPI _RST failed\n"); - return -ENOTTY; + ret = -ENOTTY; } - return 0; + pci_reset_iommu_done(dev); + return ret; } bool acpi_pci_power_manageable(struct pci_dev *dev) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b14dd064006cc..52461d952cbf1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +97,23 @@ bool pci_reset_supported(struct pci_dev *dev) return dev->reset_methods[0] != 0; } +/* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS before + * initiating a reset. Notify the iommu driver that enabled ATS. + */ +int pci_reset_iommu_prepare(struct pci_dev *dev) +{ + if (pci_ats_supported(dev)) + return iommu_dev_reset_prepare(&dev->dev); + return 0; +} + +void pci_reset_iommu_done(struct pci_dev *dev) +{ + if (pci_ats_supported(dev)) + iommu_dev_reset_done(&dev->dev); +} + #ifdef CONFIG_PCI_DOMAINS int pci_domains_supported = 1; #endif @@ -4478,13 +4497,22 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); */ int pcie_flr(struct pci_dev *dev) { + int ret = 0; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); + /* Have to call it after waiting for pending DMA transaction */ + ret = pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); if (dev->imm_ready) - return 0; + goto done; /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within @@ -4493,7 +4521,10 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + ret = pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_reset_iommu_done(dev); + return ret; } EXPORT_SYMBOL_GPL(pcie_flr); @@ -4521,6 +4552,7 @@ EXPORT_SYMBOL_GPL(pcie_reset_flr); static int pci_af_flr(struct pci_dev *dev, bool probe) { + int ret = 0; int pos; u8 cap; @@ -4547,10 +4579,17 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) PCI_AF_STATUS_TP << 8)) pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); + /* Have to call it after waiting for pending DMA transaction */ + ret = pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); if (dev->imm_ready) - return 0; + goto done; /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, @@ -4560,7 +4599,10 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) */ msleep(100); - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + ret = pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_reset_iommu_done(dev); + return ret; } /** @@ -4581,6 +4623,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) static int pci_pm_reset(struct pci_dev *dev, bool probe) { u16 csr; + int ret; if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4595,6 +4638,12 @@ static int pci_pm_reset(struct pci_dev *dev, bool probe) if (dev->current_state != PCI_D0) return -EINVAL; + ret = pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + csr &= ~PCI_PM_CTRL_STATE_MASK; csr |= PCI_D3hot; pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); @@ -4605,7 +4654,9 @@ static int pci_pm_reset(struct pci_dev *dev, bool probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + ret = pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + pci_reset_iommu_done(dev); + return ret; } /** @@ -5060,6 +5111,12 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) if (rc) return -ENOTTY; + rc = pci_reset_iommu_prepare(dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU\n"); + return rc; + } + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { val = reg; } else { @@ -5074,6 +5131,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, reg); + pci_reset_iommu_done(dev); return rc; } diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 214ed060ca1b3..891d9e5a97e93 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4226,6 +4226,22 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { { 0 } }; +static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, + const struct pci_dev_reset_methods *i) +{ + int ret; + + ret = pci_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + ret = i->reset(dev, probe); + pci_reset_iommu_done(dev); + return ret; +} + /* * These device-specific reset methods are here rather than in a driver * because when a host assigns a device to a guest VM, the host may need @@ -4240,7 +4256,7 @@ int pci_dev_specific_reset(struct pci_dev *dev, bool probe) i->vendor == (u16)PCI_ANY_ID) && (i->device == dev->device || i->device == (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return __pci_dev_specific_reset(dev, probe, i); } return -ENOTTY; -- 2.43.0