From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0E8DC433EF for ; Tue, 11 Jan 2022 14:39:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h/VUag/zYfyXnheYZxU/DTW+G0J6/Evx/lytIBxDQkc=; b=vjiMOXMg0BKQga eSjxW5E9Xt9+tSMiYglkmT5J8O7wAN6sHNCT16so64mY3h6ZOcUaGgL0Alxl6tYucqhQKZIdxsC6h qZFSYC3osuxcmca3Ly5JdT6k8CmqZV4V5q6ingax9ZAxq/2P0it1n5pQWeOuwNfxZWJRT7KQ9hcVS dIY9QYkpJQtrRVGkz32QwFzOQVDCHIBV/apnw6LvZKBpXcnJJFJXLutGFDsIpO8F+K5+3iZykTIBu +z62FvhM7E1UO7ujrePVmEhuTpOIg25AX8Pm7pKyJSGE6hXvd1Ut8zm3+88UiNjDGX60hlVDoB6s0 doVPEtzh/uSF7qnn0e9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7IIK-00GZwy-6x; Tue, 11 Jan 2022 14:38:40 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n7IIG-00GZwR-P9 for linux-arm-kernel@lists.infradead.org; Tue, 11 Jan 2022 14:38:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 922941FB; Tue, 11 Jan 2022 06:38:33 -0800 (PST) Received: from [10.57.68.71] (unknown [10.57.68.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B1FF53F774; Tue, 11 Jan 2022 06:38:32 -0800 (PST) Message-ID: Date: Tue, 11 Jan 2022 14:38:28 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: Re: [bootwrapper PATCH 06/13] aarch64: initialize SCTLR_ELx for the boot-wrapper Content-Language: en-GB To: Mark Rutland , linux-arm-kernel@lists.infradead.org Cc: andre.przywara@arm.com, Jaxson.Han@arm.com, Wei.Chen@arm.com References: <20220111130653.2331827-1-mark.rutland@arm.com> <20220111130653.2331827-7-mark.rutland@arm.com> From: Robin Murphy In-Reply-To: <20220111130653.2331827-7-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220111_063836_923008_CCE938AA X-CRM114-Status: GOOD ( 16.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-01-11 13:06, Mark Rutland wrote: > The SCTLR_ELx registers contain fields which are UNKNOWN or > IMPLEMENTATION DEFINED out of reset. This includes SCTLR_ELx.EE, which > defines the endianness of memory accesses (e.g. reads from literal > pools). Due to this, portions of boot-wrapper code are not guaranteed > top work correctly. Nit: "to" > Rework the startup code to explicitly initialize SCTLR_ELx for the > exception level the boot-wrapper was entered at. When entered at EL2 > it's necessary to first initialise HCR_EL2.E2H as this affects the RESx > behaviour of bits in SCTLR_EL2, and also aliases SCTLR_EL1 to SCTLR_EL2, > which would break the initialization performed in jump_kernel. > > As we plan to eventually support the highest implemented EL being any of > EL3/EL2/EL1, code is added to handle all of these exception levels, even > though we do not currently support starting at EL1. > > We'll initialize other registers in subsequent patches. > > Signed-off-by: Mark Rutland [...] > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 1053414..f0edd2a 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -14,6 +14,32 @@ > #define MPIDR_ID_BITS 0xff00ffffff > > #define CURRENTEL_EL3 (3 << 2) > +#define CURRENTEL_EL2 (2 << 2) > +#define CURRENTEL_EL1 (1 << 2) > + > +/* > + * RES1 bit definitions definitions as of ARM DDI 0487G.b > + * > + * These includes bits which are RES1 in some configurations. > + */ > +#define SCTLR_EL3_RES1 (1 << 29 | 1 << 28 | 1 << 23 | 1 << 22 | \ > + 1 << 18 | 1 << 16 | 1 << 11 | 1 << 5 | 1 << 4) > + > +#define SCTLR_EL2_RES1 (1 << 29 | 1 << 28 | 1 << 23 | 1 << 22 | \ > + 1 << 18 | 1 << 16 | 1 << 11 | 1 << 5 | 1 << 4) > + > +#define SCTLR_EL1_RES1 (1 << 29 | 1 << 28 | 1 << 23 | 1 << 22 | \ > + 1 << 11 | 1 << 8 | 1 << 7 | 1 << 4) > + > +#define HCR_EL2_RES1 (1 << 1) Maybe use the new BIT() macro in these? I reckon that would be more readable overall. Robin. > + > +/* > + * Initial register values required for the boot-wrapper to run out-of-reset. > + */ > +#define SCTLR_EL3_RESET SCTLR_EL3_RES1 > +#define SCTLR_EL2_RESET SCTLR_EL2_RES1 > +#define SCTLR_EL1_RESET SCTLR_EL1_RES1 > +#define HCR_EL2_RESET HCR_EL2_RES1 > > #define ID_AA64PFR0_EL1_GIC BITS(27, 24) > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel