From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A1F0C64E7A for ; Tue, 1 Dec 2020 06:06:08 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ADE882087D for ; Tue, 1 Dec 2020 06:06:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="wIhFHtSW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ADE882087D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ujyz1nu8Dtcri1oyRZv80WCwi8pOsEr5cBxs69CLEoc=; b=wIhFHtSWGemzMkz2j1VZMziEo 3P2e14jGBVaMd371YRZp5mvnVg3Yza+Lzv4OsGQO9p1Qaduk4G8f52pWEAstnunhxXyaH+dr4o9GI zirF1Q7dv+TLfwvksfChxhSpFxHODR7nZqCqkDs82gM46W+K7Yc67b3FZZqF5enXqa0tEOZbFXmHz 2mfWisRSTGhozQuGuSs3r8pFrlE3TDRXPmCTs+P1Ku8MlrBGukYUtyaKt1iCXmCbmUC0hfHoTY9Mh HnuNE3wXhegMgzPq2prjOinmPwPW/kzitdR4NT8WMX2shsIp+0LaO+n0HIaJa2/VuNV/StvRDoRIP 6TJWZrAmQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjym9-0007M4-Ak; Tue, 01 Dec 2020 06:04:33 +0000 Received: from szxga03-in.huawei.com ([45.249.212.189]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjym5-0007LV-A4 for linux-arm-kernel@lists.infradead.org; Tue, 01 Dec 2020 06:04:30 +0000 Received: from dggeme768-chm.china.huawei.com (unknown [172.30.72.57]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4ClWkW0TyDz4yHX; Tue, 1 Dec 2020 14:03:47 +0800 (CST) Received: from [10.174.186.123] (10.174.186.123) by dggeme768-chm.china.huawei.com (10.3.19.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1913.5; Tue, 1 Dec 2020 14:04:18 +0800 Subject: Re: [RFC PATCH 3/3] KVM: arm64: Add usage of stage 2 fault lookup level in user_mem_abort() To: Will Deacon References: <20201130121847.91808-1-wangyanan55@huawei.com> <20201130121847.91808-4-wangyanan55@huawei.com> <20201130134913.GC24837@willie-the-truck> From: "wangyanan (Y)" Message-ID: Date: Tue, 1 Dec 2020 14:04:18 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201130134913.GC24837@willie-the-truck> Content-Language: en-US X-Originating-IP: [10.174.186.123] X-ClientProxiedBy: dggeme716-chm.china.huawei.com (10.1.199.112) To dggeme768-chm.china.huawei.com (10.3.19.114) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201201_010429_861996_E6827B67 X-CRM114-Status: GOOD ( 20.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiangkunkun@huawei.com, Gavin Shan , Suzuki K Poulose , Marc Zyngier , wangjingyi11@huawei.com, Quentin Perret , lushenming@huawei.com, linux-kernel@vger.kernel.org, yezengruan@huawei.com, James Morse , linux-arm-kernel@lists.infradead.org, Catalin Marinas , yuzenghui@huawei.com, wanghaibin.wang@huawei.com, zhukeqian1@huawei.com, Julien Thierry Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 2020/11/30 21:49, Will Deacon wrote: > On Mon, Nov 30, 2020 at 08:18:47PM +0800, Yanan Wang wrote: >> If we get a FSC_PERM fault, just using (logging_active && writable) to determine >> calling kvm_pgtable_stage2_map(). There will be two more cases we should consider. >> >> (1) After logging_active is configged back to false from true. When we get a >> FSC_PERM fault with write_fault and adjustment of hugepage is needed, we should >> merge tables back to a block entry. This case is ignored by still calling >> kvm_pgtable_stage2_relax_perms(), which will lead to an endless loop and guest >> panic due to soft lockup. >> >> (2) We use (FSC_PERM && logging_active && writable) to determine collapsing >> a block entry into a table by calling kvm_pgtable_stage2_map(). But sometimes >> we may only need to relax permissions when trying to write to a page other than >> a block. In this condition, using kvm_pgtable_stage2_relax_perms() will be fine. >> >> The ISS filed bit[1:0] in ESR_EL2 regesiter indicates the stage2 lookup level >> at which a D-abort or I-abort occured. By comparing granule of the fault lookup >> level with vma_pagesize, we can strictly distinguish conditions of calling >> kvm_pgtable_stage2_relax_perms() or kvm_pgtable_stage2_map(), and the above >> two cases will be well considered. >> >> Suggested-by: Keqian Zhu >> Signed-off-by: Yanan Wang >> --- >> arch/arm64/include/asm/esr.h | 1 + >> arch/arm64/include/asm/kvm_emulate.h | 5 +++++ >> arch/arm64/kvm/mmu.c | 11 +++++++++-- >> 3 files changed, 15 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h >> index 22c81f1edda2..85a3e49f92f4 100644 >> --- a/arch/arm64/include/asm/esr.h >> +++ b/arch/arm64/include/asm/esr.h >> @@ -104,6 +104,7 @@ >> /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ >> #define ESR_ELx_FSC (0x3F) >> #define ESR_ELx_FSC_TYPE (0x3C) >> +#define ESR_ELx_FSC_LEVEL (0x03) >> #define ESR_ELx_FSC_EXTABT (0x10) >> #define ESR_ELx_FSC_SERROR (0x11) >> #define ESR_ELx_FSC_ACCESS (0x08) >> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h >> index 5ef2669ccd6c..2e0e8edf6306 100644 >> --- a/arch/arm64/include/asm/kvm_emulate.h >> +++ b/arch/arm64/include/asm/kvm_emulate.h >> @@ -350,6 +350,11 @@ static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vc >> return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE; >> } >> >> +static __always_inline u8 kvm_vcpu_trap_get_fault_level(const struct kvm_vcpu *vcpu) >> +{ >> + return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_LEVEL; >> +{ >> + >> static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu) >> { >> switch (kvm_vcpu_trap_get_fault(vcpu)) { >> diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c >> index 1a01da9fdc99..75814a02d189 100644 >> --- a/arch/arm64/kvm/mmu.c >> +++ b/arch/arm64/kvm/mmu.c >> @@ -754,10 +754,12 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, >> gfn_t gfn; >> kvm_pfn_t pfn; >> bool logging_active = memslot_is_logging(memslot); >> - unsigned long vma_pagesize; >> + unsigned long fault_level = kvm_vcpu_trap_get_fault_level(vcpu); >> + unsigned long vma_pagesize, fault_granule; >> enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R; >> struct kvm_pgtable *pgt; >> >> + fault_granule = 1UL << ARM64_HW_PGTABLE_LEVEL_SHIFT(fault_level); > I like the idea, but is this macro reliable for stage-2 page-tables, given > that we could have a concatenated pgd? > > Will > . Yes, it's fine even when we have a concatenated pgd table. No matter a concatenated pgd will be made or not, the initial lookup level (start _level) is set in VTCR_EL2 register. The MMU hardware walker will know the start_level according to information in VTCR_EL2. This idea runs well in practice on host where ia_bits is 40, PAGE_SIZE is 4k, and a concatenated pgd is made for guest stage2. According to the kernel info printed, the start_level is 1, and stage 2 translation runs as expected. Yanan _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel