From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9F91C433DB for ; Thu, 4 Feb 2021 09:31:31 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63A9964F48 for ; Thu, 4 Feb 2021 09:31:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63A9964F48 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From: Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GSbX6jvqYPnZ5H3bl8/htw7+SzTTcDVSctmCFZpOquw=; b=Zc75PqmJ9NVhb9vx6u92u2Xj+ huWmpk9NXCXjCYbJweL70kfe2AXKbCQbVTZ6LLHPxEwc2FmJZOHWmedwH4je953xW9Z1Z1rfQSD2m Ijj5i5TLRfrUQUgaNlKClPmoXuNS+9byx2TNAGWkC8ksghakEg330qS3CdJ487pte1XbIfcqovkRo xs+giWdoSqHEhOf+5KNRCy0/D/7FM3cBUAIUANjdT9j5vdjlryGy262zBkPle7Dg/x2IEuWAAEuSI NtIr3WmMMublTAnCDPf2URSUD5qiq1p24xDlUOoi5pn4lgFActIT4IvcwRiRj2tW0CbmBwmTjaibD +gtModHWA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7axr-0000dm-5N; Thu, 04 Feb 2021 09:30:15 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7axo-0000dH-7k for linux-arm-kernel@lists.infradead.org; Thu, 04 Feb 2021 09:30:13 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A01DA64F48; Thu, 4 Feb 2021 09:30:10 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1l7axk-00BwvW-Bz; Thu, 04 Feb 2021 09:30:08 +0000 MIME-Version: 1.0 Date: Thu, 04 Feb 2021 09:30:08 +0000 From: Marc Zyngier To: Will Deacon Subject: Re: [PATCH v6 06/21] arm64: Move VHE-specific SPE setup to mutate_to_vhe() In-Reply-To: <20210203211319.GA19694@willie-the-truck> References: <20210201115637.3123740-1-maz@kernel.org> <20210201115637.3123740-7-maz@kernel.org> <20210203211319.GA19694@willie-the-truck> User-Agent: Roundcube Webmail/1.4.10 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: will@kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, dbrazdil@google.com, alexandru.elisei@arm.com, ardb@kernel.org, jingzhangos@google.com, pajay@qti.qualcomm.com, psodagud@codeaurora.org, sramana@codeaurora.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210204_043012_440367_328CF5A3 X-CRM114-Status: GOOD ( 23.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Jing Zhang , Prasad Sodagudi , Srinivas Ramana , Suzuki K Poulose , Catalin Marinas , linux-kernel@vger.kernel.org, Ard Biesheuvel , James Morse , Julien Thierry , Ajay Patil , kernel-team@android.com, David Brazdil , Alexandru Elisei , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 2021-02-03 21:13, Will Deacon wrote: > Hi Marc, > > On Mon, Feb 01, 2021 at 11:56:22AM +0000, Marc Zyngier wrote: >> There isn't much that a VHE kernel needs on top of whatever has >> been done for nVHE, so let's move the little we need to the >> VHE stub (the SPE setup), and drop the init_el2_state macro. >> >> No expected functional change. >> >> Signed-off-by: Marc Zyngier >> Acked-by: David Brazdil >> Acked-by: Catalin Marinas >> --- >> arch/arm64/kernel/hyp-stub.S | 28 +++++++++++++++++++++++++--- >> 1 file changed, 25 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm64/kernel/hyp-stub.S >> b/arch/arm64/kernel/hyp-stub.S >> index 373ed2213e1d..6b5c73cf9d52 100644 >> --- a/arch/arm64/kernel/hyp-stub.S >> +++ b/arch/arm64/kernel/hyp-stub.S >> @@ -92,9 +92,6 @@ SYM_CODE_START_LOCAL(mutate_to_vhe) >> msr hcr_el2, x0 >> isb >> >> - // Doesn't do much on VHE, but still, worth a shot >> - init_el2_state vhe >> - >> // Use the EL1 allocated stack, per-cpu offset >> mrs x0, sp_el1 >> mov sp, x0 >> @@ -107,6 +104,31 @@ SYM_CODE_START_LOCAL(mutate_to_vhe) >> mrs_s x0, SYS_VBAR_EL12 >> msr vbar_el1, x0 >> >> + // Fixup SPE configuration, if supported... >> + mrs x1, id_aa64dfr0_el1 >> + ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4 >> + mov x2, xzr >> + cbz x1, skip_spe >> + >> + // ... and not owned by EL3 >> + mrs_s x0, SYS_PMBIDR_EL1 >> + and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) >> + cbnz x0, skip_spe >> + >> + // Let the SPE driver in control of the sampling >> + mrs_s x0, SYS_PMSCR_EL1 >> + bic x0, x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT) >> + bic x0, x0, #(1 << SYS_PMSCR_EL2_PA_SHIFT) >> + msr_s SYS_PMSCR_EL1, x0 > > Why do we need to touch pmscr_el1 at all? The SPE driver should take > care of > that, no? If you drop the pmscr_el1 accesses, I think you can drop the > pmbidr_el1 check as well. That's definitely a brain fart, and is what we need on the nVHE path, not here. Doing the same thing twice isn't exactly helpful. > And actually, then why even check dfr0? Doing the > bic for the mdcr_el1.e2pb bits is harmless. > >> + mov x2, #MDCR_EL2_TPMS >> + >> +skip_spe: >> + // For VHE, use EL2 translation and disable access from EL1 >> + mrs x0, mdcr_el2 >> + bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) >> + orr x0, x0, x2 >> + msr mdcr_el2, x0 > > Doesn't this undo the setting of mdcr_el2.hpmn if SPE is not present or > unavailable? (This wouldn't be an issue if we removed the skip_spe > paths > altogether). I don't think it does. We only clear the E2PB bits (harmless, as you point out above), and OR something that is either 0 (no SPE) or MDCR_EL2_TPMS. In any case, the HPMN bits are preserved (having been set during the nVHE setup). I think the following patch addresses the above issue, which I'll squash with the original patch. Please shout if I missed anything. Thanks, M. diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index aa7e8d592295..3e08dcc924b5 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -115,29 +115,9 @@ SYM_CODE_START_LOCAL(mutate_to_vhe) mrs_s x0, SYS_VBAR_EL12 msr vbar_el1, x0 - // Fixup SPE configuration, if supported... - mrs x1, id_aa64dfr0_el1 - ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4 - mov x2, xzr - cbz x1, skip_spe - - // ... and not owned by EL3 - mrs_s x0, SYS_PMBIDR_EL1 - and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) - cbnz x0, skip_spe - - // Let the SPE driver in control of the sampling - mrs_s x0, SYS_PMSCR_EL1 - bic x0, x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT) - bic x0, x0, #(1 << SYS_PMSCR_EL2_PA_SHIFT) - msr_s SYS_PMSCR_EL1, x0 - mov x2, #MDCR_EL2_TPMS - -skip_spe: - // For VHE, use EL2 translation and disable access from EL1 + // Use EL2 translations for SPE and disable access from EL1 mrs x0, mdcr_el2 bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) - orr x0, x0, x2 msr mdcr_el2, x0 // Transfer the MM state from EL1 to EL2 -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel