From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7CF1C433F5 for ; Fri, 28 Jan 2022 17:13:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=PtB0ujZY2yHqenNuXhDzu5oIs74tkBPOkM4VVr8Wg8E=; b=zeJEaY4E+BQK/p3L9ZU/AuYyVL gW/oljGWOW7Jpd6QTfpNEH5RqeOzy0DL9sscnf//+2sfxp/XXsxtVKMwScilflduLiy92nXrWR+lY DgMnPEyAZw4jKiAkosx7m+BAbQlr90YgvMZcsVNXjeYs3bFR4/lO/ilKCLtOWLXxpDOVDCZiyB4cp Xq52WGPfcIT5fUiw3Yx4eESCudPcEQhdwnyJrlC9zEaVO/bpDVYW0ZHFWITTz29W3CrvyIl+NppQM gM8twg514XahYLQXh8WFHnwQijyq1VAiFBJMeUD2ziLlsSJ/2BS7qTfCNCEasIa3a2XtUBKRPjF/5 K1laRAGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDUnH-0039U1-Ty; Fri, 28 Jan 2022 17:12:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDUnD-0039TF-Bh for linux-arm-kernel@lists.infradead.org; Fri, 28 Jan 2022 17:12:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 030BC113E; Fri, 28 Jan 2022 09:12:10 -0800 (PST) Received: from [10.57.10.50] (unknown [10.57.10.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F5BE3F793; Fri, 28 Jan 2022 09:12:09 -0800 (PST) Subject: Re: [PATCH v1 4/4] arm64/mte: Add userspace interface for enabling asymmetric mode To: Mark Brown , Catalin Marinas , Will Deacon Cc: Joey Gouly , Branislav Rankov , linux-arm-kernel@lists.infradead.org References: <20220127195712.748150-1-broonie@kernel.org> <20220127195712.748150-5-broonie@kernel.org> From: Vincenzo Frascino Message-ID: Date: Fri, 28 Jan 2022 17:12:20 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20220127195712.748150-5-broonie@kernel.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220128_091211_543242_762A4069 X-CRM114-Status: GOOD ( 37.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/27/22 7:57 PM, Mark Brown wrote: > The architecture provides an asymmetric mode for MTE where tag mismatches > are checked asynchronously for reads but synchronously for loads. MTE3 checks synchronously the reads and asynchronously the writes. Nit: Please use load/store or read/write. > Allow userspace processes to select this and make it available as a default mode > via the existing per-CPU sysfs interface. > > Since there PR_MTE_TCF_ values are a bitmask (allowing the kernel to choose > between the multiple modes) and there are no free bits adjacent to the > existing PR_MTE_TCF_ bits the set of bits used to specify the mode becomes > disjoint. Programs using the new interface should be aware of this and > programs that do not use it will not see any change in behaviour. > > When userspace requests two possible modes but the system default for the > CPU is the third mode (eg, default is synchronous but userspace requests > either asynchronous or asymmetric) the preference order is: > > ASYMM > ASYNC > SYNC > > This situation is not currently possible since there are only two modes and > it is mandatory to have a system default so there could be no ambiguity and > there is no ABI change. The chosen order is basically arbitrary as we do not > have a clear metric for what is better here. > > If userspace requests specifically asymmetric mode via the prctl() and the > system does not support it then we will return an error, this mirrors > how we handle the case where userspace enables MTE on a system that does > not support MTE at all and the behaviour that will be seen if running on > an older kernel that does not support userspace use of asymmetric mode. > > Attempts to set asymmetric mode as the default mode will result in an error > if the system does not support it. > > Signed-off-by: Mark Brown Otherwise: Reviewed-by: Vincenzo Frascino > --- > arch/arm64/include/asm/processor.h | 1 + > arch/arm64/kernel/mte.c | 12 +++++++++++- > arch/arm64/kernel/process.c | 5 ++++- > include/uapi/linux/prctl.h | 4 +++- > 4 files changed, 19 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h > index 6f41b65f9962..73e38d9a540c 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -21,6 +21,7 @@ > > #define MTE_CTRL_TCF_SYNC (1UL << 16) > #define MTE_CTRL_TCF_ASYNC (1UL << 17) > +#define MTE_CTRL_TCF_ASYMM (1UL << 18) > > #ifndef __ASSEMBLY__ > > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index fa4001fee12a..fb777d8fea32 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -215,7 +215,9 @@ static void mte_update_sctlr_user(struct task_struct *task) > * set bits and map into register values determines our > * default order. > */ > - if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC) > + if (resolved_mte_tcf & MTE_CTRL_TCF_ASYMM) > + sctlr |= SCTLR_EL1_TCF0_ASYMM; > + else if (resolved_mte_tcf & MTE_CTRL_TCF_ASYNC) > sctlr |= SCTLR_EL1_TCF0_ASYNC; > else if (resolved_mte_tcf & MTE_CTRL_TCF_SYNC) > sctlr |= SCTLR_EL1_TCF0_SYNC; > @@ -306,6 +308,8 @@ long set_mte_ctrl(struct task_struct *task, unsigned long arg) > mte_ctrl |= MTE_CTRL_TCF_ASYNC; > if (arg & PR_MTE_TCF_SYNC) > mte_ctrl |= MTE_CTRL_TCF_SYNC; > + if (arg & PR_MTE_TCF_ASYMM) > + mte_ctrl |= MTE_CTRL_TCF_ASYMM; > > task->thread.mte_ctrl = mte_ctrl; > if (task == current) { > @@ -334,6 +338,8 @@ long get_mte_ctrl(struct task_struct *task) > ret |= PR_MTE_TCF_ASYNC; > if (mte_ctrl & MTE_CTRL_TCF_SYNC) > ret |= PR_MTE_TCF_SYNC; > + if (mte_ctrl & MTE_CTRL_TCF_ASYMM) > + ret |= PR_MTE_TCF_ASYMM; > > return ret; > } > @@ -481,6 +487,8 @@ static ssize_t mte_tcf_preferred_show(struct device *dev, > return sysfs_emit(buf, "async\n"); > case MTE_CTRL_TCF_SYNC: > return sysfs_emit(buf, "sync\n"); > + case MTE_CTRL_TCF_ASYMM: > + return sysfs_emit(buf, "asymm\n"); > default: > return sysfs_emit(buf, "???\n"); > } > @@ -496,6 +504,8 @@ static ssize_t mte_tcf_preferred_store(struct device *dev, > tcf = MTE_CTRL_TCF_ASYNC; > else if (sysfs_streq(buf, "sync")) > tcf = MTE_CTRL_TCF_SYNC; > + else if (cpus_have_cap(ARM64_MTE_ASYMM) && sysfs_streq(buf, "asymm")) > + tcf = MTE_CTRL_TCF_ASYMM; > else > return -EINVAL; > > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index 5369e649fa79..941cfa7117b9 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -635,7 +635,10 @@ long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg) > return -EINVAL; > > if (system_supports_mte()) > - valid_mask |= PR_MTE_TCF_MASK | PR_MTE_TAG_MASK; > + valid_mask |= PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC \ > + | PR_MTE_TAG_MASK; > + if (cpus_have_cap(ARM64_MTE_ASYMM)) > + valid_mask |= PR_MTE_TCF_ASYMM; > > if (arg & ~valid_mask) > return -EINVAL; > diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h > index e998764f0262..4ae2b21e4066 100644 > --- a/include/uapi/linux/prctl.h > +++ b/include/uapi/linux/prctl.h > @@ -238,7 +238,9 @@ struct prctl_mm_map { > # define PR_MTE_TCF_NONE 0UL > # define PR_MTE_TCF_SYNC (1UL << 1) > # define PR_MTE_TCF_ASYNC (1UL << 2) > -# define PR_MTE_TCF_MASK (PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC) > +# define PR_MTE_TCF_ASYMM (1UL << 19) > +# define PR_MTE_TCF_MASK (PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC | \ > + PR_MTE_TCF_ASYMM) > /* MTE tag inclusion mask */ > # define PR_MTE_TAG_SHIFT 3 > # define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) > -- Regards, Vincenzo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel