From: Jeremy Kerr <jk@codeconstruct.com.au>
To: Dylan Hung <dylan_hung@aspeedtech.com>,
alexandre.belloni@bootlin.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
joel@jms.id.au, andrew@aj.id.au, p.zabel@pengutronix.de,
linux-i3c@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Cc: BMC-SW@aspeedtech.com, kobedylan@gmail.com
Subject: Re: [PATCH 0/3] Add Aspeed AST2600 I3C support
Date: Wed, 09 Aug 2023 08:28:57 +0800 [thread overview]
Message-ID: <a670192024911f7f2d676e245f5f240e9ed5126b.camel@codeconstruct.com.au> (raw)
In-Reply-To: <d8d577e91779e045d5a2c7d701f65133a15b5d64.camel@codeconstruct.com.au>
Hi Dylan,
> - with no changes needed to any bindings. I haven't needed any other
> resets; are there per-controller resets specified in the HW docs you
> have?
... keeping in mind the reset control that the aspeed SCU driver
already provides for you, when you enable the appropriate clock gate:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-aspeed.c#n224
Cheers,
Jeremy
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next prev parent reply other threads:[~2023-08-09 0:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-08 15:42 [PATCH 0/3] Add Aspeed AST2600 I3C support Dylan Hung
2023-08-08 15:42 ` [PATCH 1/3] ARM: dts: pinctrl-aspeed-g6: Add I3C1 and I3C2 control pins Dylan Hung
2023-08-08 15:42 ` [PATCH 2/3] dt-bindings: i3c: ast2600: Add resets and reset-names Dylan Hung
2023-08-08 15:59 ` Krzysztof Kozlowski
2023-08-08 15:42 ` [PATCH 3/3] i3c: ast2600: Add reset deassertion for global registers Dylan Hung
2023-08-08 16:00 ` Krzysztof Kozlowski
2023-08-09 0:07 ` [PATCH 0/3] Add Aspeed AST2600 I3C support Jeremy Kerr
2023-08-09 0:28 ` Jeremy Kerr [this message]
2023-08-09 2:46 ` Dylan Hung
[not found] ` <TYZPR06MB65674B8AA26D959254101A749C12A@TYZPR06MB6567.apcprd06.prod.outlook.com>
2023-08-09 3:12 ` Jeremy Kerr
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