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From: Eric Auger <eric.auger@redhat.com>
To: Marc Zyngier <maz@kernel.org>,
	kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Mark Brown <broonie@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Will Deacon <will@kernel.org>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Chase Conklin <chase.conklin@arm.com>,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
	Darren Hart <darren@os.amperecomputing.com>,
	Miguel Luis <miguel.luis@oracle.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH 06/27] arm64: Add debug registers affected by HDFGxTR_EL2
Date: Fri, 14 Jul 2023 16:47:20 +0200	[thread overview]
Message-ID: <a69eda3e-d255-1eb4-c6d2-7ba02ba02468@redhat.com> (raw)
In-Reply-To: <20230712145810.3864793-7-maz@kernel.org>

Hi Marc,

On 7/12/23 16:57, Marc Zyngier wrote:
> The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
> related registers. Add their encodings (and only that, because
> we really don't care about what these registers actually do at
> this stage).
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 76289339b43b..9dfd127be55a 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -194,6 +194,84 @@
>  #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)*
>  #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)*
>  
> +#define SYS_BRBINF_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))*
> +#define SYS_BRBINFINJ_EL1		sys_reg(2, 1, 9, 1, 0)*
> +#define SYS_BRBSRC_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))*
> +#define SYS_BRBSRCINJ_EL1		sys_reg(2, 1, 9, 1, 1)*
> +#define SYS_BRBTGT_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))*
> +#define SYS_BRBTGTINJ_EL1		sys_reg(2, 1, 9, 1, 2)*
> +#define SYS_BRBTS_EL1			sys_reg(2, 1, 9, 0, 2)*
> +
> +#define SYS_BRBCR_EL1			sys_reg(2, 1, 9, 0, 0)*
> +#define SYS_BRBFCR_EL1			sys_reg(2, 1, 9, 0, 1)*
> +#define SYS_BRBIDR0_EL1			sys_reg(2, 1, 9, 2, 0)*
> +
> +#define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
> +#define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
I cannot find this one - which is duplicated by the way - in DDI0487Jaa
> +#define SYS_TRCACATR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))*
> +#define SYS_TRCACVR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))*
> +#define SYS_TRCAUTHSTATUS		sys_reg(2, 1, 7, 14, 6)*
> +#define SYS_TRCAUXCTLR			sys_reg(2, 1, 0, 6, 0)*
> +#define SYS_TRCBBCTLR			sys_reg(2, 1, 0, 15, 0)*
> +#define SYS_TRCCCCTLR			sys_reg(2, 1, 0, 14, 0)*
> +#define SYS_TRCCIDCCTLR0		sys_reg(2, 1, 3, 0, 2)*
> +#define SYS_TRCCIDCCTLR1		sys_reg(2, 1, 3, 1, 2)*
> +#define SYS_TRCCIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 0)*
> +#define SYS_TRCCLAIMCLR			sys_reg(2, 1, 7, 9, 6)*
> +#define SYS_TRCCLAIMSET			sys_reg(2, 1, 7, 8, 6)*
> +#define SYS_TRCCNTCTLR(m)		sys_reg(2, 1, 0, (4 | (m & 3)), 5)*
> +#define SYS_TRCCNTRLDVR(m)		sys_reg(2, 1, 0, (0 | (m & 3)), 5)*
> +#define SYS_TRCCNTVR(m)			sys_reg(2, 1, 0, (8 | (m & 3)), 5)*
> +#define SYS_TRCCONFIGR			sys_reg(2, 1, 0, 4, 0)*
> +#define SYS_TRCDEVARCH			sys_reg(2, 1, 7, 15, 6)*
> +#define SYS_TRCDEVID			sys_reg(2, 1, 7, 2, 7)*
> +#define SYS_TRCEVENTCTL0R		sys_reg(2, 1, 0, 8, 0)*
> +#define SYS_TRCEVENTCTL1R		sys_reg(2, 1, 0, 9, 0)*
> +#define SYS_TRCEXTINSELR(m)		sys_reg(2, 1, 0, (8 | (m & 3)), 4)*
> +#define SYS_TRCIDR0			sys_reg(2, 1, 0, 8, 7)*
> +#define SYS_TRCIDR10			sys_reg(2, 1, 0, 2, 6)*
> +#define SYS_TRCIDR11			sys_reg(2, 1, 0, 3, 6)*
> +#define SYS_TRCIDR12			sys_reg(2, 1, 0, 4, 6)*
> +#define SYS_TRCIDR13			sys_reg(2, 1, 0, 5, 6)*
> +#define SYS_TRCIDR1			sys_reg(2, 1, 0, 9, 7)*
> +#define SYS_TRCIDR2			sys_reg(2, 1, 0, 10, 7)*
> +#define SYS_TRCIDR3			sys_reg(2, 1, 0, 11, 7)*
> +#define SYS_TRCIDR4			sys_reg(2, 1, 0, 12, 7)*
> +#define SYS_TRCIDR5			sys_reg(2, 1, 0, 13, 7)*
> +#define SYS_TRCIDR6			sys_reg(2, 1, 0, 14, 7)*
> +#define SYS_TRCIDR7			sys_reg(2, 1, 0, 15, 7)*
> +#define SYS_TRCIDR8			sys_reg(2, 1, 0, 0, 6)*
> +#define SYS_TRCIDR9			sys_reg(2, 1, 0, 1, 6)*
> +#define SYS_TRCIMSPEC0			sys_reg(2, 1, 0, 0, 7)*
> +#define SYS_TRCIMSPEC(m)		sys_reg(2, 1, 0, (m & 7), 7)*
> +#define SYS_TRCITEEDCR			sys_reg(2, 1, 0, 2, 1)
I cannot find this one in D18-1 or elsewhere in DDI0487Jaa
> +#define SYS_TRCOSLSR			sys_reg(2, 1, 1, 1, 4)*
> +#define SYS_TRCPRGCTLR			sys_reg(2, 1, 0, 1, 0)*
> +#define SYS_TRCQCTLR			sys_reg(2, 1, 0, 1, 1)*
> +#define SYS_TRCRSCTLR(m)		sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))*
> +#define SYS_TRCRSR			sys_reg(2, 1, 0, 10, 0)*
> +#define SYS_TRCSEQEVR(m)		sys_reg(2, 1, 0, (m & 3), 4)*
> +#define SYS_TRCSEQRSTEVR		sys_reg(2, 1, 0, 6, 4)*
> +#define SYS_TRCSEQSTR			sys_reg(2, 1, 0, 7, 4)*
> +#define SYS_TRCSSCCR(m)			sys_reg(2, 1, 1, (m & 7), 2)*
> +#define SYS_TRCSSCSR(m)			sys_reg(2, 1, 1, (8 | (m & 7)), 2)*
> +#define SYS_TRCSSPCICR(m)		sys_reg(2, 1, 1, (m & 7), 3)*
> +#define SYS_TRCSTALLCTLR		sys_reg(2, 1, 0, 11, 0)*
> +#define SYS_TRCSTATR			sys_reg(2, 1, 0, 3, 0)*
> +#define SYS_TRCSYNCPR			sys_reg(2, 1, 0, 13, 0)*
> +#define SYS_TRCTRACEIDR			sys_reg(2, 1, 0, 0, 1)*
> +#define SYS_TRCTSCTLR			sys_reg(2, 1, 0, 12, 0)*
> +#define SYS_TRCVICTLR			sys_reg(2, 1, 0, 0, 2)*
> +#define SYS_TRCVIIECTLR			sys_reg(2, 1, 0, 1, 2)*
> +#define SYS_TRCVIPCSSCTLR		sys_reg(2, 1, 0, 3, 2)*
> +#define SYS_TRCVISSCTLR			sys_reg(2, 1, 0, 2, 2)*
> +#define SYS_TRCVMIDCCTLR0		sys_reg(2, 1, 3, 2, 2)*
> +#define SYS_TRCVMIDCCTLR1		sys_reg(2, 1, 3, 3, 2)*
> +#define SYS_TRCVMIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 1)*
> +
> +/* ETM */
> +#define SYS_TRCOSLAR			sys_reg(2, 1, 1, 0, 4)
not able to locate this one either. I see the bit of HDFGWTR_EL2 though

Eric
> +
>  #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
>  #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
>  #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)


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  reply	other threads:[~2023-07-14 14:48 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-12 14:57 [PATCH 00/27] KVM: arm64: NV trap forwarding infrastructure Marc Zyngier
2023-07-12 14:57 ` [PATCH 01/27] arm64: Add missing VA CMO encodings Marc Zyngier
2023-07-12 14:57 ` [PATCH 02/27] arm64: Add missing ERX*_EL1 encodings Marc Zyngier
2023-07-12 14:57 ` [PATCH 03/27] arm64: Add missing DC ZVA/GVA/GZVA encodings Marc Zyngier
2023-07-12 14:57 ` [PATCH 04/27] arm64: Add TLBI operation encodings Marc Zyngier
2023-07-12 14:57 ` [PATCH 05/27] arm64: Add AT " Marc Zyngier
2023-07-12 14:57 ` [PATCH 06/27] arm64: Add debug registers affected by HDFGxTR_EL2 Marc Zyngier
2023-07-14 14:47   ` Eric Auger [this message]
2023-07-14 16:09     ` Marc Zyngier
2023-07-19  8:48   ` Suzuki K Poulose
2023-07-19 11:00   ` Suzuki K Poulose
2023-07-27 15:42     ` Marc Zyngier
2023-07-12 14:57 ` [PATCH 07/27] arm64: Add missing BRB/CFP/DVP/CPP instructions Marc Zyngier
2023-07-18 17:30   ` Miguel Luis
2023-07-12 14:57 ` [PATCH 08/27] arm64: Fix HFGxTR_EL2 field naming Marc Zyngier
2023-07-12 14:57 ` [PATCH 09/27] arm64: Add HDFGRTR_EL2 and HDFGWTR_EL2 layouts Marc Zyngier
2023-07-12 16:59   ` Mark Brown
2023-07-12 14:57 ` [PATCH 10/27] arm64: Add feature detection for fine grained traps Marc Zyngier
2023-07-14  9:57   ` Eric Auger
2023-07-12 14:57 ` [PATCH 11/27] KVM: arm64: Correctly handle ACCDATA_EL1 traps Marc Zyngier
2023-07-12 14:57 ` [PATCH 12/27] KVM: arm64: Add missing HCR_EL2 trap bits Marc Zyngier
2023-07-12 14:57 ` [PATCH 13/27] KVM: arm64: nv: Add FGT registers Marc Zyngier
2023-07-12 14:57 ` [PATCH 14/27] KVM: arm64: Restructure FGT register switching Marc Zyngier
2023-07-12 17:15   ` Mark Brown
2023-07-12 20:06     ` Marc Zyngier
2023-07-12 21:15       ` Mark Brown
     [not found]   ` <fd0d93ae-1ae5-b53e-ccb7-04d78f7c31d9@redhat.com>
     [not found]     ` <87y1j3qgpu.wl-maz@kernel.org>
2023-07-28 17:22       ` Eric Auger
2023-07-12 14:57 ` [PATCH 15/27] KVM: arm64: nv: Add trap forwarding infrastructure Marc Zyngier
2023-07-12 14:57 ` [PATCH 16/27] KVM: arm64: nv: Add trap forwarding for HCR_EL2 Marc Zyngier
2023-07-13 14:05   ` Eric Auger
2023-07-13 15:53     ` Marc Zyngier
2023-07-14 10:10       ` Marc Zyngier
2023-07-14 15:06         ` Eric Auger
2023-07-14 16:28           ` Marc Zyngier
2023-07-14 14:58       ` Eric Auger
2023-07-12 14:58 ` [PATCH 17/27] KVM: arm64: nv: Expose FEAT_EVT to nested guests Marc Zyngier
2023-07-12 14:58 ` [PATCH 18/27] KVM: arm64: nv: Add trap forwarding for MDCR_EL2 Marc Zyngier
2023-07-13 17:34   ` Eric Auger
2023-07-14 11:13     ` Marc Zyngier
2023-07-12 14:58 ` [PATCH 19/27] KVM: arm64: nv: Add trap forwarding for CNTHCTL_EL2 Marc Zyngier
     [not found]   ` <9739cab9-c058-ec5f-ac15-7d708aef4e85@redhat.com>
2023-07-27 15:38     ` Marc Zyngier
2023-07-12 14:58 ` [PATCH 20/27] KVM: arm64: nv: Add trap forwarding for HFGxTR_EL2 Marc Zyngier
2023-07-12 14:58 ` [PATCH 21/27] KVM: arm64: nv: Add trap forwarding for HFGITR_EL2 Marc Zyngier
2023-07-12 14:58 ` [PATCH 22/27] KVM: arm64: nv: Add trap forwarding for HDFGxTR_EL2 Marc Zyngier
2023-07-12 14:58 ` [PATCH 23/27] KVM: arm64: nv: Add SVC trap forwarding Marc Zyngier
2023-07-12 14:58 ` [PATCH 24/27] KVM: arm64: nv: Add switching support for HFGxTR/HDFGxTR Marc Zyngier
2023-07-12 14:58 ` [PATCH 25/27] KVM: arm64: nv: Expose FGT to nested guests Marc Zyngier
2023-07-12 14:58 ` [PATCH 26/27] KVM: arm64: Move HCRX_EL2 switch to load/put on VHE systems Marc Zyngier
2023-07-12 14:58 ` [PATCH 27/27] KVM: arm64: nv: Add support for HCRX_EL2 Marc Zyngier
2023-07-12 15:16 ` [PATCH 00/27] KVM: arm64: NV trap forwarding infrastructure Eric Auger
2023-07-12 15:29   ` Eric Auger
2023-07-12 15:31   ` Marc Zyngier

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