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([2600:8804:5716:d800::f01a]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-860dcbc82b5sm3364957a34.17.2026.11.10.18.24.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 18:24:13 -0800 (PST) Message-ID: Date: Tue, 10 Nov 2026 20:24:11 -0600 X-Archived-By: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clocksource/drivers/timer-mediatek: Don't override the arch timer sched_clock To: Chen-Yu Tsai , Daniel Lezcano , Thomas Gleixner , Matthias Brugger , AngeloGioacchino Del Regno Cc: Luca Leonardo Scorcia , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20261109120757.847266-1-wenst@chromium.org> Content-Language: en-US From: Ryan Brue In-Reply-To: <20261109120757.847266-1-wenst@chromium.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261110_182416_117812_D4C8B8EB X-CRM114-Status: GOOD ( 11.57 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-9.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Chen-Yu, On 11/9/26 6:07 AM, Chen-Yu Tsai wrote: > Before the conversion, both drivers used TIMER_OF_DECLARE and > timer-mediatek.o is linked before arm_arch_timer.o, so the arch timer > registered last and won. On MT8173 the GPT already replaced the arch timer as sched_clock before 7a097aba7255. Every boot log I have from 7.3 on the Fire HD 10 shows the same swap, for example on 7.3.0-rc5:   [    0.000000] arch_timer: cp15 timer running at 13.00MHz (phys).   [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns   [    0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns   [    0.000366] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 147020034397 ns   [    0.000378] sched_clock: 32 bits at 13MHz, resolution 76ns, wraps every 165191050201ns and on 7.3.0-rc6:   [    0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns   [    0.000192] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 147020034397 ns   [    0.000201] sched_clock: 32 bits at 13MHz, resolution 76ns, wraps every 165191050201ns Neither kernel had changes to drivers/clocksource or kernel/time iirc. I think the reason is that timer_probe() walks the device tree nodes in order and matches each one against __timer_of_table, so link order only decides which entry a node matches, not which timer initializes first. In mt8173.dtsi the arm,armv8-timer node comes before soc/timer@10008000, so the GPT registered second then too, and with the same rate it replaced the arch timer. So what the conversion changed is when the swap happens, late enough to trigger the splat, rather than whether it happens. The patch still LGTM, and it gives MT8173 the 56-bit arch counter back. It's just the history paragraph that I wanted to give my anecdote for. On the Fire HD 10 (2017), v7.4-rc2 with this patch prints only "sched_clock: 56 bits at 13MHz", where the rc1 boot before it switched to the GPT's 32 bits. Boot, suspend/resume, and cpufreq are fine. Tested-by: Ryan Brue # on Amazon Fire HD 10 (MT8173) Thanks! Ryan Brue