[PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz

[PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz

[Marek Vasut]

The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.

There are two options of addressing this problem, either by using the
DLYB block to compensate the extra delay, or by reducing the QSPI bus
clock frequency. The former requires calibration and that is overly
complex, so opt for the second option.

Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
index 2b0ac605549d7..44ecc47085871 100644
--- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
@@ -202,7 +202,7 @@ flash0: flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-rx-bus-width = <4>;
-		spi-max-frequency = <108000000>;
+		spi-max-frequency = <50000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 	};
-- 
2.30.2


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Re: [PATCH] ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHz

[Alexandre TORGUE]

Hi Marek

On 8/9/21 2:13 PM, Marek Vasut wrote:
> The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
> which causes additional signal delay. At 108 MHz, this delay triggers
> a sporadic issue where the first bit of RX data is not received by the
> QSPI controller.
> 
> There are two options of addressing this problem, either by using the
> DLYB block to compensate the extra delay, or by reducing the QSPI bus
> clock frequency. The former requires calibration and that is overly
> complex, so opt for the second option.
> 
> Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96")
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
> Cc: linux-stm32@st-md-mailman.stormreply.com
> To: linux-arm-kernel@lists.infradead.org
> ---
>   arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
> index 2b0ac605549d7..44ecc47085871 100644
> --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
> +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
> @@ -202,7 +202,7 @@ flash0: flash@0 {
>   		compatible = "jedec,spi-nor";
>   		reg = <0>;
>   		spi-rx-bus-width = <4>;
> -		spi-max-frequency = <108000000>;
> +		spi-max-frequency = <50000000>;
>   		#address-cells = <1>;
>   		#size-cells = <1>;
>   	};
> 

Applied on stm32-next.

Thanks
Alex

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