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[66.91.136.155]) by smtp.gmail.com with ESMTPSA id w187sm23776762pfw.62.2020.01.15.16.23.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Jan 2020 16:23:43 -0800 (PST) Subject: Re: [PATCH v10 1/3] arm64: Implement archrandom.h for ARMv8.5-RNG To: Catalin Marinas , Mark Brown References: <20200110122341.8445-1-broonie@kernel.org> <20200110122341.8445-2-broonie@kernel.org> <20200114174432.GG2579@willie-the-truck> <20200115091651.GB21692@willie-the-truck> <20200115110720.GG3897@sirena.org.uk> <20200115142611.GC3429@arrakis.emea.arm.com> From: Richard Henderson Message-ID: Date: Wed, 15 Jan 2020 14:23:39 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <20200115142611.GC3429@arrakis.emea.arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200115_162346_644724_752D8A8D X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Will Deacon , linux-arm-kernel , Ard Biesheuvel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/15/20 4:26 AM, Catalin Marinas wrote: > On Wed, Jan 15, 2020 at 11:07:20AM +0000, Mark Brown wrote: >> On Wed, Jan 15, 2020 at 10:24:21AM +0100, Ard Biesheuvel wrote: >>> On Wed, 15 Jan 2020 at 10:16, Will Deacon wrote: >> >>>> I see your argument, but I was just going on the side of consistency because >>>> we're continuing to expose other features as HWCAPs when the capability is >>>> just a proxy for the cpuid field. I was in favour of stopping the addition >>>> of such HWCAPs years ago, but I couldn't convince Catalin ;) >> >>>> The way I see it, we'll soon run out of HWCAP2 bits and then we'll have >>>> our hand forced. >> >>> I don't have a strong opinion either way. >> >> Me either, or at least not enough to object to doing it - Will? >> Catalin? > > Until the ifunc resolver can work with CPUID, I think we should keep > adding HWCAPn bits. We can revisit this with the toolchain people before > introducing HWCAP3. Why would the ifunc resolver not be able to use HWCAP_CPUID? The first argument to the ifunc resolver, apparently since the beginning of time (2013-11-25 7520ff8c744a), AT_HWCAP has been passed directly as the first argument. That means HWCAP_CPUID, present in AT_HWCAP, can always be tested directly. At which point one can access architected registers, with no dynamic linker relocations, to make further decisions. Admittedly there's a trap to the OS involved, but there is *far* too much info in those registers to copy everything to HWCAPn. The current state of affairs, as of glibc-2.30, is that the first argument is augmented to include a _IFUNC_ARG_HWCAP bit, which indicates the presence of a second argument, a pointer to struct __ifunc_arg_t. This struct does include a size field, allowing the struct to be extended in future. That said, speaking as a toolchain guy, you should conserve HWCAP2 bits so that, by preference, you do not need to introduce AT_HWCAP3. Or at least delay adding it. r~ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel