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Wed, 13 Sep 2023 23:05:35 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 13 Sep 2023 23:05:35 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 13 Sep 2023 23:05:35 -0500 Received: from [10.24.68.114] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38E45VtF120507; Wed, 13 Sep 2023 23:05:32 -0500 Message-ID: Date: Thu, 14 Sep 2023 09:35:31 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH] soc: ti: k3-socinfo: Fix the silicon revision misprint Content-Language: en-US To: Nishanth Menon CC: Thejasvi Konduru , , , Santosh Shilimkar , Tero Kristo , Grygorii Strashko , Lokesh Vutla , Apurva Nandan , Udit Kumar References: <20230607080349.26671-1-t-konduru@ti.com> <20230607104304.iengykppptr3fxe6@reflected> <20230913112823.prv5dmasvv4nt6qv@nuclear> From: Neha Malcom Francis In-Reply-To: <20230913112823.prv5dmasvv4nt6qv@nuclear> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230913_210546_862721_55B16DF1 X-CRM114-Status: GOOD ( 21.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Nishanth On 13/09/23 16:58, Nishanth Menon wrote: > On 12:07-20230912, Neha Malcom Francis wrote: > > [...] > >>>> +void >>>> +k3_chipinfo_silicon_rev(unsigned int variant, >>>> + struct soc_device_attribute *soc_dev_attr) >>>> +{ >>>> + const char *family_name = soc_dev_attr->family; >>>> + int j721e_lookup_arr_size = ARRAY_SIZE(soc_revision_j721e); >>>> + >>>> + if (!strcmp(family_name, "J721E") && variant < j721e_lookup_arr_size) { >>>> + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%s", soc_revision_j721e[variant]); >>>> + } else { >>>> + variant++; >>>> + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "SR%x.0", variant); >>>> + } >>> >>> I am not comfortable with if else here. Why not extend k3_soc_id >>> structure to include the variant LuT? Are there exceptions to this rule >>> (Say AM65x?), those would make sense to handle with a compare against >>> the partno? >>> >> >> Trying to revive this patch, I see what you are saying is similar to the way >> detection has already been implemented in U-Boot (drivers/soc/soc_ti_k3.c) >> if I'm not mistaken. > > Yes. > >> >> But I can't find any existing exception to this "family --> version" rule >> that forces us to use "partno --> version". Checked through all AM65x device >> TRMs available in ti.com; all seem to use common partno. So maybe I am not >> on the same page, did you mean something else? > > https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf > CTRLMMR_WKUP_JTAGID:: VARIANT field: SR2.0: 1h SR1.0: 0h > Latest data sheet: https://www.ti.com/lit/ds/symlink/am6548.pdf > indicates SR 2.1 > > How is this detected? Detection of the ".x" bit is still a WIP and needs some alignment internally before I can add that patch. So for now, working on cleaning up the known issues of the driver. > > What I indicated is a LUT table similar to > https://git.ti.com/cgit/k3conf/k3conf/tree/common/socinfo.c#n382 > > This allows a switch statement to handle custom SR handling schemes or > use LUT with variants that use VARIANT field to handle things properly. > This makes sense, will work on the patch accordingly. Thanks! > [...] -- Thanking You Neha Malcom Francis _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel