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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae353ca1619sm854280966b.149.2025.07.01.05.10.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jul 2025 05:10:42 -0700 (PDT) Message-ID: Date: Tue, 1 Jul 2025 14:10:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/8] arm64: dts: qcom: ipq5424: Add NSS clock controller node To: Luo Jie , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Philipp Zabel , Richard Cochran , Konrad Dybcio , Catalin Marinas , Will Deacon , Anusha Rao Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, quic_pavir@quicinc.com References: <20250627-qcom_ipq5424_nsscc-v2-0-8d392f65102a@quicinc.com> <20250627-qcom_ipq5424_nsscc-v2-7-8d392f65102a@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAxMDA3NiBTYWx0ZWRfX2Jn28azCqxDX 4XQ0IeNBa3v+nSloE0BHhCeJJXQLsu8tNfmYpY+E3cL3l17E7+mCb5DX5Yo/3CpOUm02/yLLRv/ m5d0nSU6SWabHNiS5y/t14G74kFseenxqJk+LDUyx8rmRSnLsI1wZYh72WDnuJI4MV2uJcWB0ZH XEAn91eYQBwrVu2l1d9JqCQNVv920nJ9DlHnezkZSwybVOsIAftvphSIUShbgs6kcl9ZU6IzXxi g+eoVaNM+xyMkxQ/2qawvlM12tDtf+fjIC5U9BFrykwowbZKxsp7RlatxThjOo8w+uodhmFf3uE dcJbcv7VgiIXYdidcIvs3ZS/gcg/fnbkPxxCbjpcaFx/Tq3wLATfaoHBGKf7nbpAbMwLUZBwWCE zE2jtIInIsIJAwqT7mLir1kv+8xrE4bx+AgpMCFS46FnltvTQek2fmfVSFGWmxAQdwFpPkbt X-Proofpoint-ORIG-GUID: FYAs_zF1m_sy5aFiNMtdrtPLm-cfqF27 X-Authority-Analysis: v=2.4 cv=EuHSrTcA c=1 sm=1 tr=0 ts=6863d045 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=fKQzr7EGRj+VoE0XNsDNvQ==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=ovtazKSSlfofSAFZHdsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: FYAs_zF1m_sy5aFiNMtdrtPLm-cfqF27 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-01_02,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 malwarescore=0 mlxscore=0 phishscore=0 spamscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507010076 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250701_051046_687157_791060DF X-CRM114-Status: GOOD ( 18.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 01-Jul-25 14:08, Luo Jie wrote: > > > On 6/28/2025 12:27 AM, Konrad Dybcio wrote: >> On 6/27/25 2:09 PM, Luo Jie wrote: >>> NSS clock controller provides the clocks and resets to the networking >>> hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and >>> UNIPHY (PCS) blocks. >>> >>> Signed-off-by: Luo Jie >>> --- >>>   arch/arm64/boot/dts/qcom/ipq5424.dtsi | 30 ++++++++++++++++++++++++++++++ >>>   1 file changed, 30 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi >>> index 2eea8a078595..eb4aa778269c 100644 >>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi >>> @@ -730,6 +730,36 @@ frame@f42d000 { >>>               }; >>>           }; >>>   +        clock-controller@39b00000 { >>> +            compatible = "qcom,ipq5424-nsscc"; >>> +            reg = <0 0x39b00000 0 0x800>; >> >> size = 0x100_000 >> >> with that: >> >> Reviewed-by: Konrad Dybcio >> >> Konrad > > I initially thought that a block size of 0x800 would be sufficient, as > it covers the maximum address range needed for the clock configurations. > However, the NSS clock controller block actually occupies an address > range of 0x80000. I will update this to 0x80000 in the next version. > Thank you for your feedback. 0x80_000 excludes the wrapper region. Please mark it as the entire 0x100_000 that it occupies, no matter if there's anything in there Konrad