From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A024C433E0 for ; Mon, 4 Jan 2021 10:05:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 204A020780 for ; Mon, 4 Jan 2021 10:05:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 204A020780 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; 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Mon, 04 Jan 2021 10:03:52 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwMiM-0006R0-K2 for linux-arm-kernel@lists.infradead.org; Mon, 04 Jan 2021 10:03:51 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7D5D020769; Mon, 4 Jan 2021 10:03:49 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1kwMiJ-005Blr-DU; Mon, 04 Jan 2021 10:03:47 +0000 MIME-Version: 1.0 Date: Mon, 04 Jan 2021 10:03:47 +0000 From: Marc Zyngier To: Samuel Holland Subject: Re: [PATCH v3 03/10] irqchip/sun6i-r: Use a stacked irqchip driver In-Reply-To: <8c1eaddd-577b-9c2a-aa6a-9ee716178d4a@sholland.org> References: <20210103103101.33603-1-samuel@sholland.org> <20210103103101.33603-4-samuel@sholland.org> <875z4el0p2.wl-maz@kernel.org> <66a7eb24-66c7-d5e6-1235-aa6846c5eef2@sholland.org> <8735zikvyq.wl-maz@kernel.org> <8c1eaddd-577b-9c2a-aa6a-9ee716178d4a@sholland.org> User-Agent: Roundcube Webmail/1.4.9 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: samuel@sholland.org, tglx@linutronix.de, robh+dt@kernel.org, mripard@kernel.org, wens@csie.org, jernej.skrabec@siol.net, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, megous@megous.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210104_050350_815710_AAF461E0 X-CRM114-Status: GOOD ( 27.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ondrej Jirman , devicetree@vger.kernel.org, Jernej Skrabec , Catalin Marinas , Russell King , Maxime Ripard , linux-kernel@vger.kernel.org, Chen-Yu Tsai , Rob Herring , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021-01-04 03:46, Samuel Holland wrote: > On 1/3/21 7:10 AM, Marc Zyngier wrote: >> On Sun, 03 Jan 2021 12:08:43 +0000, >> Samuel Holland wrote: >>> >>> On 1/3/21 5:27 AM, Marc Zyngier wrote: [...] >>> For edge interrupts, don't you want to ack as early as possible, >>> before the handler clears the source of the interrupt? That way if a >>> second interrupt comes in while you're handling the first one, you >>> don't ack the second one without handling it? >> >> It completely depends on what this block does. If, as I expect, it >> latches the interrupt, then it needs clearing after the GIC has acked >> the incoming interrupt. > > Yes, there is an internal S/R latch. > - For edge interrupts, the latch is set once for each pulse. > - For level interrupts, it gets set continuously as long as the > pin is high/low. > - Writing a "1" to bit 0 of PENDING resets the latch. > - The output of the latch goes to the GIC. > >>>> It also begs the question: why would you want to clear the signal to >>>> the GIC on mask (or unmask)? The expectations are that a pending >>>> interrupt is preserved across a mask/unmask sequence. >>> >>> I hadn't thought about anything masking the IRQ outside of the >>> handler; but you're right, this breaks that case. I'm trying to work >>> within the constraints of stacking the GIC driver, which assumes >>> handle_fasteoi_irq, so it sounds like I should switch back to >>> handle_fasteoi_ack_irq and use .irq_ack. Or based on your previous >>> paragraph, maybe I'm missing some other consideration? >> >> handle_fasteoi_ack_irq() sounds like a good match for edge >> interrupts. Do you actually need to do anything for level signals? If >> you do, piggybacking on .irq_eoi would do the trick. > > For level interrupts, I have to reset the latch (see above) after the > source of > the interrupt is cleared. Right, so that is definitely to be done in .irq_eoi, at least in the non-threaded case (as it doesn't involve masking/unmasking). > That was the bug with v2: I set IRQ_EOI_THREADED so .irq_eoi would run > after the > thread. But with GICv2 EOImode==0, that blocked other interrupts from > being > received during the IRQ thread. Which is why I moved it to .irq_unmask > and > removed the flag: so .irq_eoi runs at the end of the hardirq > (unblocking further > interrupts at the GIC), and .irq_unmask resets the latch at the end of > the thread. > > With the flag removed, but still clearing the latch in .irq_eoi, every > edge IRQ edge? Didn't you mean level here? Edge interrupts really should clear the latch in .irq_ack. > was followed by a second, spurious IRQ after the thread finished. > > Does that make sense? It does. It is a bit of a kludge, but hey, silly HW (if only this could be turned into a bypass, it'd all be simpler). To sum it up, this is what I'd expect to see: For edge interrupts: - clear latch in .irq_ack and .irq_set_irqchip_state(PENDING) - interrupt flow set to fasteoi_ack For level interrupts - clear latch in .irq_eoi (non-threaded) and .irq_unmask (threaded) - interrupt flow set to fasteoi (though leaving to the _ack version should not hurt). Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel