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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jie Gan <jie.gan@oss.qualcomm.com>, Rob Herring <robh@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	James Clark <james.clark@linaro.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
	Mao Jinlong <jinlong.mao@oss.qualcomm.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU
Date: Thu, 18 Dec 2025 11:17:57 +0100	[thread overview]
Message-ID: <a9537dc9-c767-4909-8b1c-6e939ce4f3fc@kernel.org> (raw)
In-Reply-To: <dfa43a63-ca14-4dd7-a7ab-acd95748a8b9@oss.qualcomm.com>

On 12/12/2025 02:12, Jie Gan wrote:
> 
> 
> On 12/11/2025 9:37 PM, Rob Herring wrote:
>> On Thu, Dec 11, 2025 at 02:10:44PM +0800, Jie Gan wrote:
>>> Add an interrupt property to CTCU device. The interrupt will be triggered
>>> when the data size in the ETR buffer exceeds the threshold of the
>>> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
>>> of CTCU device will enable the interrupt.
>>>
>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> Reviewed-by: Mike Leach <mike.leach@linaro.org>
>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>> ---
>>>   .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml    | 17 +++++++++++++++++
>>>   1 file changed, 17 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> index c969c16c21ef..90f88cc6cd3e 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
>>> @@ -39,6 +39,16 @@ properties:
>>>       items:
>>>         - const: apb
>>>   
>>> +  interrupts:
>>> +    items:
>>> +      - description: Byte cntr interrupt for the first etr device
>>> +      - description: Byte cntr interrupt for the second etr device
>>> +
>>> +  interrupt-names:
>>> +    items:
>>> +      - const: etrirq0
>>> +      - const: etrirq1
>>
>> Names are kind of pointless when it is just foo<index>.
> 
> Hi Rob,
> 
> I was naming them as etr0/etr1. Are these names acceptable?

Obviously irq is redundant, but how does etr0 solves the problem of
calling it foo0?

I don't think you really read Rob's comment.

> The interrupts are assigned exclusively to a specific ETR device.
> 
> But Suzuki is concerned that this might cause confusion because the ETR 
> device is named randomly in the driver. Suzuki suggested using ‘port-0’ 
> and ‘port-1’ and would also like to hear your feedback on these names.

There is no confusion here. Writing bindings luckily clarifies this what
the indices in the array mean.

> 
> Usually, the probe sequence follows the order of the addresses. In our 
> specification, ‘ETR0’ is always probed before ‘ETR1’ because its address 
> is lower.

How is this even relevant? You are answering to something completely
different, so I don't think you really tried to understand review.



Best regards,
Krzysztof


  reply	other threads:[~2025-12-18 10:18 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-11  6:10 [PATCH v8 0/8] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-12-11  6:10 ` [PATCH v8 1/8] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-12-11  6:10 ` [PATCH v8 2/8] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-12-13 12:38   ` kernel test robot
2025-12-18 17:50   ` Suzuki K Poulose
2025-12-19  9:24     ` Jie Gan
2025-12-11  6:10 ` [PATCH v8 3/8] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2025-12-11  6:10 ` [PATCH v8 4/8] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations Jie Gan
2025-12-11  6:10 ` [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-12-11  7:27   ` Rob Herring (Arm)
2025-12-11  7:35     ` Jie Gan
2025-12-11 13:37   ` Rob Herring
2025-12-12  1:12     ` Jie Gan
2025-12-18 10:17       ` Krzysztof Kozlowski [this message]
2025-12-18 23:19         ` Suzuki K Poulose
2025-12-19  2:05           ` Jie Gan
2025-12-19  9:54             ` Suzuki K Poulose
2025-12-22  6:58               ` Jie Gan
2025-12-22  9:17                 ` Jie Gan
2025-12-11  6:10 ` [PATCH v8 6/8] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-12-11  6:10 ` [PATCH v8 7/8] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2025-12-11  6:10 ` [PATCH v8 8/8] arm64: dts: qcom: lemans: Add interrupts to CTCU device Jie Gan

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