From: Daniel Golle <daniel@makrotopia.org>
To: Jakub Kicinski <kuba@kernel.org>
Cc: Felix Fietkau <nbd@nbd.name>, Sean Wang <sean.wang@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Florian Fainelli <f.fainelli@gmail.com>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH net v2 4/5] net: ethernet: mtk_eth_soc: net: revise NETSYSv3 hardware configuration
Date: Thu, 17 Apr 2025 16:45:14 +0100 [thread overview]
Message-ID: <aAEiCjdJdsqH6EAU@makrotopia.org> (raw)
In-Reply-To: <20250417081055.1bda2ff6@kernel.org>
On Thu, Apr 17, 2025 at 08:10:55AM -0700, Jakub Kicinski wrote:
> On Wed, 16 Apr 2025 01:51:42 +0100 Daniel Golle wrote:
> > + /* PSE should not drop port8, port9 and port13 packets from WDMA Tx */
> > + mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
> > +
> > + /* PSE should drop packets to port8, port9 and port13 on WDMA Rx ring full */
>
> nit: please try to wrap at 80 chars. There's really no need to go over
> on comments. Some of us stick to 80 char terminals.
Too late now to send another revision...
> > [...]
> > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > index 39709649ea8d1..eaa96c8483b70 100644
> > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> > @@ -151,7 +151,12 @@
> > #define PSE_FQFC_CFG1 0x100
> > #define PSE_FQFC_CFG2 0x104
> > #define PSE_DROP_CFG 0x108
> > -#define PSE_PPE0_DROP 0x110
> > +#define PSE_PPE_DROP(x) (0x110 + ((x) * 0x4))
> > +
> > +/* PSE Last FreeQ Page Request Control */
> > +#define PSE_DUMY_REQ 0x10C
>
> This really looks like misspelling of DUMMY, is it really supposed
> to have one 'M' ?
I also thought that when I first saw that and have told MediaTek engineers
about it, they told me that the register is called like that also in their
datasheet and hence they want the name to be consistent in the driver.
next prev parent reply other threads:[~2025-04-17 16:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-16 0:50 [PATCH net v2 1/5] net: ethernet: mtk_eth_soc: reapply mdc divider on reset Daniel Golle
2025-04-16 0:51 ` [PATCH net v2 2/5] net: ethernet: mtk_eth_soc: correct the max weight of the queue limit for 100Mbps Daniel Golle
2025-04-16 0:51 ` [PATCH net v2 3/5] net: ethernet: mtk_eth_soc: revise QDMA packet scheduler settings Daniel Golle
2025-04-16 0:51 ` [PATCH net v2 4/5] net: ethernet: mtk_eth_soc: net: revise NETSYSv3 hardware configuration Daniel Golle
2025-04-17 15:10 ` Jakub Kicinski
2025-04-17 15:45 ` Daniel Golle [this message]
2025-04-17 15:59 ` Jakub Kicinski
2025-04-17 16:16 ` Daniel Golle
2025-04-16 0:52 ` [PATCH net v2 5/5] net: ethernet: mtk_eth_soc: convert cap_bit in mtk_eth_muxc struct to u64 Daniel Golle
2025-04-17 15:13 ` Jakub Kicinski
2025-04-17 15:57 ` Daniel Golle
2025-04-17 15:31 ` [PATCH net v2 1/5] net: ethernet: mtk_eth_soc: reapply mdc divider on reset patchwork-bot+netdevbpf
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