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From: Niklas Cassel <cassel@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com,
	heiko@sntech.de, manivannan.sadhasivam@linaro.org,
	robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH 3/3] PCI: dw-rockchip: Unify link status checks with FIELD_GET
Date: Tue, 22 Apr 2025 14:24:16 +0200	[thread overview]
Message-ID: <aAeKcEfyDS1ImynJ@ryzen> (raw)
In-Reply-To: <7716b76f-be79-4ed1-b8d2-29258cb250ab@163.com>

On Tue, Apr 22, 2025 at 07:50:50PM +0800, Hans Zhang wrote:
> 
> 
> On 2025/4/22 19:39, Niklas Cassel wrote:
> > On Tue, Apr 22, 2025 at 07:28:30PM +0800, Hans Zhang wrote:
> > > Link-up detection manually checked PCIE_LINKUP bits across RC/EP modes,
> > > leading to code duplication. Centralize the logic using FIELD_GET. This
> > > removes redundancy and abstracts hardware-specific bit masking, ensuring
> > > consistent link state handling.
> > > 
> > > Signed-off-by: Hans Zhang <18255117159@163.com>
> > > ---
> > >   drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++++----------
> > >   1 file changed, 5 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > index cdc8afc6cfc1..2b26060af5c2 100644
> > > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > > @@ -196,10 +196,7 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci)
> > >   	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
> > >   	u32 val = rockchip_pcie_get_ltssm(rockchip);
> > > -	if ((val & PCIE_LINKUP) == PCIE_LINKUP)
> > > -		return 1;
> > > -
> > > -	return 0;
> > > +	return FIELD_GET(PCIE_LINKUP_MASK, val) == 3;
> > 
> > While I like the idea of your patch, here you are replacing something that
> > is easy to read (PCIE_LINKUP) with a magic value, which IMO is a step in
> > the wrong direction.
> > 
> 
> Hi Niklas,
> 
> Thank you very much for your reply. How about I add another macro
> definition?
> 
> #define PCIE_LINKUP 3

Yes, adding another macro for it is what I meant.


Kind regards,
Niklas


  reply	other threads:[~2025-04-22 13:36 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-22 11:28 [PATCH 0/3] PCI: dw-rockchip: Reorganize register and bitfield definitions Hans Zhang
2025-04-22 11:28 ` [PATCH 1/3] PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG Hans Zhang
2025-04-22 11:35   ` Niklas Cassel
2025-04-22 11:28 ` [PATCH 2/3] PCI: dw-rockchip: Reorganize register and bitfield definitions Hans Zhang
2025-04-22 11:47   ` Niklas Cassel
2025-04-22 11:51     ` Hans Zhang
2025-04-22 12:30   ` Niklas Cassel
2025-04-22 12:39     ` Hans Zhang
2025-04-22 16:03     ` Hans Zhang
2025-04-22 11:28 ` [PATCH 3/3] PCI: dw-rockchip: Unify link status checks with FIELD_GET Hans Zhang
2025-04-22 11:39   ` Niklas Cassel
2025-04-22 11:50     ` Hans Zhang
2025-04-22 12:24       ` Niklas Cassel [this message]
2025-04-22 12:29         ` Hans Zhang
2025-04-22 11:35 ` [PATCH 0/3] PCI: dw-rockchip: Reorganize register and bitfield definitions Hans Zhang

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