[PATCH 2/2] arm64: dts: rockchip: add SATA nodes to RK3576

Nicolas Frattaroli
2025-04-24T20:22:33Z

The Rockchip RK3576 features two SATA nodes. The first, sata0, is behind
combphy0, which muxes between pcie0 and sata0.

The second, sata1, is behind combphy1, which muxes between pcie1, sata1
and usb_drd1_dwc3.

I've only been able to test sata0 on my board, but it appears to work
just fine.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index ebb5fc8bb8b1363127b9d3782801c4a79b678a92..6e27d744acad2111616eaf4807aea1eac4f00c7f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1334,6 +1334,36 @@ gmac1_mtl_tx_setup: tx-queues-config {
};
};

+ sata0: sata@2a240000 {
+ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
+ reg = <0x0 0x2a240000 0x0 0x1000>;
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ <&cru CLK_RXOOB0>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ phys = <&combphy0_ps PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ sata1: sata@2a250000 {
+ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
+ reg = <0x0 0x2a250000 0x0 0x1000>;
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+ <&cru CLK_RXOOB1>;
+ clock-names = "sata", "pmalive", "rxoob";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ phys = <&combphy1_psu PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ dma-coherent;
+ status = "disabled";
+ };
+
ufshc: ufshc@2a2d0000 {
compatible = "rockchip,rk3576-ufshc";
reg = <0x0 0x2a2d0000 0x0 0x10000>,

--
2.49.0