From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 019FDC3ABC3 for ; Fri, 9 May 2025 13:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BBDHFZZkigRRbWS8CLOiO9XMVfxvmKOMZYUDb+/K1A4=; b=YoA4Okh15WFy4nLFkvIo56iQsy t4BP1wkcscN9GSqSsZF0R0sEkzyebBh5gltezupD52guLgIWIvpJPYIDJDpXEHKQKo11t1OW3kRVq w7LAMnlOs5Qy/jSq/DD8k1IfxqtwAOFNnqa1tdP619QksO6/Oq5UXluMK0Y7+3NWdmiIcGcCFmdZt 4c0DSv74LeBTPcGkVtPoo5y0Ex5O3grCbkFnIqqkinLyL8FUL7cnzWl22qyVLGhmoyyUE40bc9HaN 9vQbEytiIE3rKClTyFwLVbZIvX5Qc7NVoRQzNj9B4UIJWVSB7WIQtytp2WqWWbRtPvlSFWzfxiT7z l6whpsrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uDO2r-00000003og9-2zdm; Fri, 09 May 2025 13:45:45 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uDN8k-00000003ddj-37ID for linux-arm-kernel@lists.infradead.org; Fri, 09 May 2025 12:47:47 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 9694FA41865; Fri, 9 May 2025 12:47:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D4DBC4CEEF; Fri, 9 May 2025 12:47:38 +0000 (UTC) Date: Fri, 9 May 2025 13:47:36 +0100 From: Catalin Marinas To: Ankit Agrawal Cc: Jason Gunthorpe , Oliver Upton , Sean Christopherson , Marc Zyngier , "joey.gouly@arm.com" , "suzuki.poulose@arm.com" , "yuzenghui@huawei.com" , "will@kernel.org" , "ryan.roberts@arm.com" , "shahuang@redhat.com" , "lpieralisi@kernel.org" , "david@redhat.com" , Aniket Agashe , Neo Jia , Kirti Wankhede , "Tarun Gupta (SW-GPU)" , Vikram Sethi , Andy Currid , Alistair Popple , John Hubbard , Dan Williams , Zhi Wang , Matt Ochs , Uday Dhoke , Dheeraj Nigam , Krishnakant Jaju , "alex.williamson@redhat.com" , "sebastianene@google.com" , "coltonlewis@google.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "ardb@kernel.org" , "akpm@linux-foundation.org" , "gshan@redhat.com" , "linux-mm@kvack.org" , "ddutile@redhat.com" , "tabba@google.com" , "qperret@google.com" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags Message-ID: References: <20250423130323.GE1648741@nvidia.com> <20250429141437.GC2260709@nvidia.com> <20250429164430.GD2260709@nvidia.com> <20250429181926.GE2260709@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250509_054746_854213_93A5617C X-CRM114-Status: GOOD ( 16.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 07, 2025 at 03:26:05PM +0000, Ankit Agrawal wrote: > >> Unless FWB implies CTR_EL0.DIC (AFAIK, it doesn't) we may be > >> restricting some CPUs. > > > > Yes, it will further narrow the CPUs down. > > > > However, we just did this discussion for BBML2 + SMMUv3 SVA. I think > > the same argument holds. If someone is crazy enough to build a CPU > > with CXLish support and uses an old core without DIC, IDC and S2FWB > > then they are going to have a bunch of work to fix the SW to support > > it. Right now we know of no system that exists like this.. > > > > Jason > > Catalin, do you agree if I can go ahead and add the check for > ARM64_HAS_CACHE_DIC? As long as we don't leave out some hardware that has FWB but not DIC, that's fine by me. -- Catalin