From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90A1BC3ABBC for ; Fri, 9 May 2025 18:18:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/y2yQ7dUZCobPkzn0ZmHNcxkJ+stQi51pBdS9KZ57i0=; b=JAUOA0F3AzLphDoLfj3cKbo0t7 5Iusm7pmv1rdN09oM3tdYNq6KwmObQU6fDOFPg09li5vV+TjdVx2nMSRBabB7D5BOeHlBdWDymFrB /IlLYOHXyrbCZM1RmFNrpu4Sd+wA4zpSdjGA4W5dfUqR6EV4OFO9JEAqz4tk12V3HCZSdGU/HYfV7 QyjcNfnc5KzCbquRhAbyWhOCBjksEPPhQ1SwvDlSPF/ra0EFdt2EDbpnJptBddiBtn8Gzgd0w6u2/ jDXIOkYabecjAQtJiqsuqXPhL4Kx9EZJbZpJCu1EM0Df5Zj724Y7VX6GpCHFocF52+eqE5lDQaKVf QJtkwXKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uDSIT-00000004YCb-2SH5; Fri, 09 May 2025 18:18:09 +0000 Received: from nyc.source.kernel.org ([2604:1380:45d1:ec00::3]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uDQDj-00000004D6u-1IPq for linux-arm-kernel@lists.infradead.org; Fri, 09 May 2025 16:05:08 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 43A9EA4C747; Fri, 9 May 2025 16:05:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC496C4CEF2; Fri, 9 May 2025 16:05:00 +0000 (UTC) Date: Fri, 9 May 2025 17:04:58 +0100 From: Catalin Marinas To: Will Deacon Cc: Ryan Roberts , =?utf-8?Q?Miko=C5=82aj?= Lenczewski , suzuki.poulose@arm.com, yang@os.amperecomputing.com, corbet@lwn.net, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, akpm@linux-foundation.org, paulmck@kernel.org, mark.rutland@arm.com, joey.gouly@arm.com, maz@kernel.org, james.morse@arm.com, broonie@kernel.org, oliver.upton@linux.dev, baohua@kernel.org, david@redhat.com, ioworker0@gmail.com, jgg@ziepe.ca, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, kevin.tian@intel.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: Re: [RESEND PATCH v6 1/3] arm64: Add BBM Level 2 cpu feature Message-ID: References: <20250428153514.55772-2-miko.lenczewski@arm.com> <20250428153514.55772-4-miko.lenczewski@arm.com> <20250506142508.GB1197@willie-the-truck> <78fec33d-fe66-4352-be11-900f456c9af3@arm.com> <20250509134904.GA5707@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250509134904.GA5707@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250509_090507_483217_C77D32D5 X-CRM114-Status: GOOD ( 30.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 09, 2025 at 02:49:05PM +0100, Will Deacon wrote: > On Tue, May 06, 2025 at 03:52:59PM +0100, Ryan Roberts wrote: > > On 06/05/2025 15:25, Will Deacon wrote: > > > This penalises large homogeneous systems and it feels unnecessary given > > > that we have the ability to check this per-CPU. Can you use > > > ARM64_CPUCAP_BOOT_CPU_FEATURE instead of ARM64_CPUCAP_SYSTEM_FEATURE > > > to solve this? > > > > We are trying to solve for the case where the boot CPU has BBML2 but a secondary > > CPU doesn't. (e.g. hetrogeneous system where boot CPU is big and secondary is > > little and does not advertise the feature. I can't remember if we proved there > > are real systems with this config - I have vague recollection that we did but my > > memory is poor...). > > > > My understanding is that for ARM64_CPUCAP_BOOT_CPU_FEATURE, "If the boot CPU > > has enabled this feature already, then every late CPU must have it". So that > > would exclude any secondary CPUs without BBML2 from coming online? > > Damn, yes, you're right. However, it still feels horribly hacky to iterate > over the online CPUs in has_bbml2_noabort() -- the cpufeature framework > has the ability to query features locally and we should be able to use > that. We're going to want that should the architecture eventually decide > on something like BBML3 for this. > > What we have with BBML2_NOABORT seems similar to an hwcap in that we only > support the capability if all CPUs have it (rejecting late CPUs without it > in that case) but we can live without it if not all of the early CPUs > have it. Unlikely hwcaps, though, we shouldn't be advertising this to > userspace and we can't derive the capability solely from the sanitised > system registers. > > I wonder if we could treat it like an erratum in some way instead? That > is, invert things so that CPUs which _don't_ have BBML2_NOABORT are > considered to have a "BBM_CONFLICT_ABORT" erratum (which we obviously > wouldn't shout about). Then we should be able to say: > > - If any of the early CPUs don't have BBML2_NOABORT, then the erratum > would be enabled and we wouln't elide BBM. > > - If a late CPU doesn't have BBML2_NOABORT then it can't come online > if the erratum isn't already enabled. > > Does that work? If not, then perhaps the cpufeature/cpuerrata code needs > some surgery for this. Ah, I should have read this thread in order. I think we can treat this as BBML2_NOABORT available as default based on ID regs and use the allow/deny-list as an erratum. -- Catalin