From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2
Date: Wed, 11 Jun 2025 00:59:48 -0300 [thread overview]
Message-ID: <aEj_NDgaFJT-oceR@geday> (raw)
In-Reply-To: <aEj7-6fMGKSXQb3J@geday>
On Wed, Jun 11, 2025 at 12:46:10AM -0300, Geraldo Nascimento wrote:
> Hi again Bjorn,
>
> Your message reminded me of something that may be important.
>
> During my debugging I had the mild impression L0s capability is not
> being cleared from Link Capabilities Register in the presence of
> "aspm-no-l0s" DT property.
>
> I can't confirm it right now but I might revisit this later on. From
> what I've seen it can only be cleared from inside the port init
> in pcie-rockchip.c and does nothing in present form.
>
> Not a clear, confirmable report but something to watch out for...
Not correct. ASPM bit for L0s is being properly cleared according
to my printk's.
Should have checked before creating noise. Sorry.
Geraldo Nascimento
>
> Regards,
> Geraldo Nascimento
prev parent reply other threads:[~2025-06-11 5:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-07 11:00 [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2 Geraldo Nascimento
2025-06-10 20:07 ` Bjorn Helgaas
2025-06-10 20:09 ` Geraldo Nascimento
2025-06-11 3:46 ` Geraldo Nascimento
2025-06-11 3:59 ` Geraldo Nascimento [this message]
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