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Fri, 13 Jun 2025 08:00:55 -0700 (PDT) Received: from geday ([2804:7f2:800b:838f::dead:c001]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b2fe1691be9sm1813060a12.68.2025.06.13.08.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 08:00:54 -0700 (PDT) Date: Fri, 13 Jun 2025 12:00:49 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v4 0/4] PCI: rockchip: Improve quality of driver Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250613_080057_590579_2F63BA51 X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 13, 2025 at 11:48:27AM -0300, Geraldo Nascimento wrote: > During a 30-day debugging-run fighting quirky PCIe devices on RK3399 > some quality improvements began to take form and this is my attempt > at upstreaming it. It will ensure maximum chance of retraining to Gen2 > 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY > they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] > without risk of locking up kernel like with present broken async > strobe TEST_WRITE. > > --- > V3 -> V4: fix TLS setting-up in Link Control and Status Register 2 and > adjust commit titles > V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's > suggestion > V1 -> V2: use standard PCIe defines as suggested by Bjorn > > Geraldo Nascimento (4): > PCI: rockchip: Drop unused custom registers and bitfields > PCI: rockchip: Set Target Link Speed before retraining > phy: rockchip-pcie: Enable all four lanes > phy: rockchip-pcie: Adjust read mask and write > > drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ > drivers/pci/controller/pcie-rockchip.h | 11 +---------- > drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++------- > 3 files changed, 14 insertions(+), 17 deletions(-) > > -- > 2.49.0 > I somehow have screwed-up threading again. Please ignore. Resending now. Geraldo Nascimento