From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1337FC77B7F for ; Fri, 27 Jun 2025 16:51:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=sVX7lo2mgR0AFr0MnFNPZxe+w9boY2xzTM+Mkj0c8rc=; b=eBF+rSNBxhDrxZ4fN8qAKit4kb 73g2zdJaqV0OxIzb2bL8MbrUHhXTuddnemjalDWjFLfPA1f42HLfSV9zzFaF26K2Dr0fHYf6Sc503 GCAz5UvmamaEQ4WwpXNRM8cAm2CozeXsxJPHZbCTyy+plOTsdS4boDFbAgaLU655Tkn/W1nLIbP9w n7Yk6ggoPdo4bigV+qF8FnI9j+F9QaBbeJGvyP5bUas/Lw+Yl1nU44bbKZtqE+M/ndsw+qbEhg3p1 FqXdHiRN9q1LSZLSwb5sOFW1oHv5vQQMtt9rG2R4TCfo3e/4Ajq0DHHSwWXSKiT0Nbh3VqMQutruO QWywSkPA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uVCHw-0000000FKZz-2m4W; Fri, 27 Jun 2025 16:50:56 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uVBHS-0000000F9eR-2idy for linux-arm-kernel@lists.infradead.org; Fri, 27 Jun 2025 15:46:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 17AF56111F; Fri, 27 Jun 2025 15:46:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88186C4CEE3; Fri, 27 Jun 2025 15:46:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751039181; bh=+sU81KHe8n8d04EFSXCcSYkBzKWoeE7L7E09uh61ogs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=FM3ksgO3WB4KcUiFvHzNoOuaUNiZDM1l7bNcQgbFX64oE9JswYJHToR49kvmIWWWw AtpHxeCV7jcbXO09wA2xj1iwQ8D8Gesmp1FKfp0VbR0lN914HJ41+y39gx/MWV4P2T p8ejIkfpdHcQ6xWgwziQcGiGLcBtz44d4Ql3/LgXYyAOg4xghf53hxLnOfGtK1l2qA zeTV+brRr9fe3TcUI/4Cpx4fPhSb4DjjeTA5qxqE77i/RBJlmaXt8FNuvynQaG2cMc sg+72Gng5IL7TW0i1oxVFDSUheHOUdHn5xaYxFUYBrFn26KB6gIC5M6lmpAosE257k jqhSp2IvQQPMA== Date: Fri, 27 Jun 2025 16:46:17 +0100 From: Will Deacon To: Ada Couprie Diaz Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Mark Rutland , Anshuman Khandual , "Luis Claudio R . Goncalves" Subject: Re: [PATCH v4 07/13] arm64: debug: split hardware breakpoint exception entry Message-ID: References: <20250620211207.773980-1-ada.coupriediaz@arm.com> <20250620211207.773980-8-ada.coupriediaz@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250620211207.773980-8-ada.coupriediaz@arm.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 20, 2025 at 10:12:01PM +0100, Ada Couprie Diaz wrote: > Currently all debug exceptions share common entry code and are routed > to `do_debug_exception()`, which calls dynamically-registered > handlers for each specific debug exception. This is unfortunate as > different debug exceptions have different entry handling requirements, > and it would be better to handle these distinct requirements earlier. > > Hardware breakpoints exceptions are generated by the hardware after user > configuration. As such, they can be exploited when training branch > predictors outside of the userspace VA range: they still need to call > `arm64_apply_bp_hardening()` if needed to mitigate against this attack. > > However, they do not need to handle the Cortex-A76 erratum #1463225 as > it only applies to single stepping exceptions. > It does not set an address in FAR_EL1 either, only the hardware > watchpoint does. > > As the hardware breakpoint handler only returns 0 and never triggers > the call to `arm64_notify_die()`, we can call it directly from > `entry-common.c`. > Split the hardware breakpoint exception entry, adjust > the function signature, and handling of the Cortex-A76 erratum to fit > the behaviour of the exception. > > Move the call to `arm64_apply_bp_hardening()` to `entry-common.c` so that > we can do it as early as possible, and only for the exceptions coming > from EL0, where it is needed. > This is safe to do as it is `noinstr`, as are all the functions it > may call. `el0_ia()` and `el0_pc()` already call it this way. > > Signed-off-by: Ada Couprie Diaz > Tested-by: Luis Claudio R. Goncalves > --- > arch/arm64/include/asm/exception.h | 1 + > arch/arm64/kernel/entry-common.c | 28 ++++++++++++++++++++++++++++ > arch/arm64/kernel/hw_breakpoint.c | 16 ++++++---------- > 3 files changed, 35 insertions(+), 10 deletions(-) Reviewed-by: Will Deacon Will