From: Frank Li <Frank.li@nxp.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Richard Zhu <hongxing.zhu@nxp.com>,
l.stach@pengutronix.de, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/3] dt-bindings: PCI: dwc: Add one more reference clock
Date: Fri, 27 Jun 2025 16:09:49 -0400 [thread overview]
Message-ID: <aF76jeV+8us82APv@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20250627-sensible-pigeon-of-reading-b021a3@krzk-bin>
On Fri, Jun 27, 2025 at 08:54:46AM +0200, Krzysztof Kozlowski wrote:
> On Thu, Jun 26, 2025 at 03:38:02PM +0800, Richard Zhu wrote:
> > Add one more reference clock "extref" to be onhalf the reference clock
> > that comes from external crystal oscillator.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> > index 34594972d8db..ee09e0d3bbab 100644
> > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> > @@ -105,6 +105,12 @@ properties:
> > define it with this name (for instance pipe, core and aux can
> > be connected to a single source of the periodic signal).
> > const: ref
> > + - description:
> > + Some dwc wrappers (like i.MX95 PCIes) have two reference clock
> > + inputs, one from internal PLL, the other from off chip crystal
> > + oscillator. Use extref clock name to be onhalf of the reference
> > + clock comes form external crystal oscillator.
>
> How internal PLL can be represented as 'ref' clock? Internal means it is
> not outside, so impossible to represent.
Internal means in side SoC, but outside PCIe controller.
>
> Where is the DTS so we can look at big picture?
imx94 pci's upstream is still on going, which quite similar with imx95.
Just board design choose external crystal.
pcie_ref_clk: clock-pcie-ref {
compatible = "gpio-gate-clock";
clocks = <&xtal25m>;
#clock-cells = <0>;
enable-gpios = <&pca9670_i2c3 7 GPIO_ACTIVE_LOW>;
};
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
clocks = <&scmi_clk IMX94_CLK_HSIO>,
<&scmi_clk IMX94_CLK_HSIOPLL>,
<&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
<&pcie_ref_clk>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ext-ref";
reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie0>;
status = "okay";
};
Frank
>
>
> Best regards,
> Krzysztof
>
next prev parent reply other threads:[~2025-06-27 20:14 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 7:38 [PATCH v4 0/3] PCI: imx6: Add external reference clock mode support Richard Zhu
2025-06-26 7:38 ` [PATCH v4 1/3] dt-bindings: PCI: dwc: Add one more reference clock Richard Zhu
2025-06-26 18:31 ` Frank Li
2025-06-26 20:52 ` Bjorn Helgaas
2025-06-27 6:54 ` Krzysztof Kozlowski
2025-06-27 20:09 ` Frank Li [this message]
2025-06-28 12:34 ` Krzysztof Kozlowski
2025-06-28 15:33 ` Frank Li
2025-06-30 8:25 ` Krzysztof Kozlowski
2025-06-30 15:08 ` Frank Li
2025-06-26 7:38 ` [PATCH v4 2/3] dt-binding: pci-imx6: Add external reference clock mode support Richard Zhu
2025-06-26 18:43 ` Frank Li
2025-06-26 20:53 ` Bjorn Helgaas
2025-06-28 12:35 ` Krzysztof Kozlowski
2025-06-26 7:38 ` [PATCH v4 3/3] PCI: imx6: " Richard Zhu
2025-06-26 18:44 ` Frank Li
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