[PATCH v3 0/2] PCI: imx6: Add external reference clock mode support

[PATCH v3 0/2] PCI: imx6: Add external reference clock mode support

[Richard Zhu]

On i.MX, the PCIe reference clock might come from either internal system
PLL or external clock source. Add the external reference clock source
for reference clock.

Main change in v3:
- Update the logic check external reference clock mode is enabled or
  not in driver codes.

Main change in v2:
- Fix yamllint warning.
- Refine the driver codes.

[PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
[PATCH v3 2/2] PCI: imx6: Add external reference clock mode support

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml |  7 ++++++-
drivers/pci/controller/dwc/pci-imx6.c                     | 20 +++++++++++++-------
2 files changed, 19 insertions(+), 8 deletions(-)

[PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Richard Zhu]

On i.MX, the PCIe reference clock might come from either internal
system PLL or external clock source.
Add the external reference clock source for reference clock.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index ca5f2970f217..c472a5daae6e 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -219,7 +219,12 @@ allOf:
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
-            - const: ref
+            - description: PCIe reference clock.
+              oneOf:
+                - description: The controller might be configured clocking
+                    coming in from either an internal system PLL or an
+                    external clock source.
+                  enum: [ref, gio]
 
 unevaluatedProperties: false
 
-- 
2.37.1

[PATCH v3 2/2] PCI: imx6: Add external reference clock mode support

[Richard Zhu]

The PCI Express reference clock of i.MX9 PCIes might come from external
clock source. Add the external reference clock mode support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 5a38cfaf989b..9309959874c0 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -149,6 +149,7 @@ struct imx_pcie {
 	struct gpio_desc	*reset_gpiod;
 	struct clk_bulk_data	*clks;
 	int			num_clks;
+	bool			enable_ext_refclk;
 	struct regmap		*iomuxc_gpr;
 	u16			msi_ctrl;
 	u32			controller_id;
@@ -241,6 +242,8 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
+	bool ext = imx_pcie->enable_ext_refclk;
+
 	/*
 	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
 	 * Through Beacon or PERST# De-assertion
@@ -259,13 +262,12 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 			IMX95_PCIE_PHY_CR_PARA_SEL,
 			IMX95_PCIE_PHY_CR_PARA_SEL);
 
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_PHY_GEN_CTRL,
-			   IMX95_PCIE_REF_USE_PAD, 0);
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_SS_RW_REG_0,
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+			   ext ? IMX95_PCIE_REF_USE_PAD : 0,
+			   IMX95_PCIE_REF_USE_PAD);
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
 			   IMX95_PCIE_REF_CLKEN,
-			   IMX95_PCIE_REF_CLKEN);
+			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
 
 	return 0;
 }
@@ -1600,7 +1602,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	struct imx_pcie *imx_pcie;
 	struct device_node *np;
 	struct device_node *node = dev->of_node;
-	int ret, domain;
+	int i, ret, domain;
 	u16 val;
 
 	imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
@@ -1651,6 +1653,10 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	if (imx_pcie->num_clks < 0)
 		return dev_err_probe(dev, imx_pcie->num_clks,
 				     "failed to get clocks\n");
+	imx_pcie->enable_ext_refclk = true;
+	for (i = 0; i < imx_pcie->num_clks; i++)
+		if (strncmp(imx_pcie->clks[i].id, "ref", 3) == 0)
+			imx_pcie->enable_ext_refclk = false;
 
 	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
 		imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
-- 
2.37.1

Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Krzysztof Kozlowski]

On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
> On i.MX, the PCIe reference clock might come from either internal
> system PLL or external clock source.
> Add the external reference clock source for reference clock.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index ca5f2970f217..c472a5daae6e 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -219,7 +219,12 @@ allOf:
>              - const: pcie_bus
>              - const: pcie_phy
>              - const: pcie_aux
> -            - const: ref
> +            - description: PCIe reference clock.
> +              oneOf:
> +                - description: The controller might be configured clocking
> +                    coming in from either an internal system PLL or an
> +                    external clock source.
> +                  enum: [ref, gio]

Internal like within PCIe or coming from other SoC block? What does
"gio" mean?

Best regards,
Krzysztof

RE: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Hongxing Zhu]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 2025年6月20日 15:53
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
> mode support
> 
> On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
> > On i.MX, the PCIe reference clock might come from either internal
> > system PLL or external clock source.
> > Add the external reference clock source for reference clock.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index ca5f2970f217..c472a5daae6e 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -219,7 +219,12 @@ allOf:
> >              - const: pcie_bus
> >              - const: pcie_phy
> >              - const: pcie_aux
> > -            - const: ref
> > +            - description: PCIe reference clock.
> > +              oneOf:
> > +                - description: The controller might be configured
> clocking
> > +                    coming in from either an internal system PLL or
> an
> > +                    external clock source.
> > +                  enum: [ref, gio]
> 
> Internal like within PCIe or coming from other SoC block? What does "gio"
> mean?
Internal means that the PCIe reference clock is coming from other
 internal SoC block, such as system PLL. "gio" is on behalf that the
reference clock comes form external crystal oscillator.

Best Regards
Richard Zhu
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Krzysztof Kozlowski]

On 20/06/2025 10:26, Hongxing Zhu wrote:
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 2025年6月20日 15:53
>> To: Hongxing Zhu <hongxing.zhu@nxp.com>
>> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
>> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
>> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
>> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
>> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
>> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
>> imx@lists.linux.dev; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
>> mode support
>>
>> On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
>>> On i.MX, the PCIe reference clock might come from either internal
>>> system PLL or external clock source.
>>> Add the external reference clock source for reference clock.
>>>
>>> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
>>> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>>> ---
>>>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
>>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> index ca5f2970f217..c472a5daae6e 100644
>>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
>>> @@ -219,7 +219,12 @@ allOf:
>>>              - const: pcie_bus
>>>              - const: pcie_phy
>>>              - const: pcie_aux
>>> -            - const: ref
>>> +            - description: PCIe reference clock.
>>> +              oneOf:
>>> +                - description: The controller might be configured
>> clocking
>>> +                    coming in from either an internal system PLL or
>> an
>>> +                    external clock source.
>>> +                  enum: [ref, gio]
>>
>> Internal like within PCIe or coming from other SoC block? What does "gio"
>> mean?
> Internal means that the PCIe reference clock is coming from other
>  internal SoC block, such as system PLL. "gio" is on behalf that the
> reference clock comes form external crystal oscillator.

Then what does "ref" mean, if gio is the clock supplied externally? We
talk here about signals coming to this chip, regardless how they are
generated.


Best regards,
Krzysztof

Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Frank Li]

On Fri, Jun 20, 2025 at 03:08:16PM +0200, Krzysztof Kozlowski wrote:
> On 20/06/2025 10:26, Hongxing Zhu wrote:
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 2025年6月20日 15:53
> >> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> >> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> >> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> >> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> >> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> >> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> >> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> >> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> >> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
> >> mode support
> >>
> >> On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
> >>> On i.MX, the PCIe reference clock might come from either internal
> >>> system PLL or external clock source.
> >>> Add the external reference clock source for reference clock.
> >>>
> >>> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> >>> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> >>> ---
> >>>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
> >>>  1 file changed, 6 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> >>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> >>> index ca5f2970f217..c472a5daae6e 100644
> >>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> >>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> >>> @@ -219,7 +219,12 @@ allOf:
> >>>              - const: pcie_bus
> >>>              - const: pcie_phy
> >>>              - const: pcie_aux
> >>> -            - const: ref
> >>> +            - description: PCIe reference clock.
> >>> +              oneOf:
> >>> +                - description: The controller might be configured
> >> clocking
> >>> +                    coming in from either an internal system PLL or
> >> an
> >>> +                    external clock source.
> >>> +                  enum: [ref, gio]
> >>
> >> Internal like within PCIe or coming from other SoC block? What does "gio"
> >> mean?
> > Internal means that the PCIe reference clock is coming from other
> >  internal SoC block, such as system PLL. "gio" is on behalf that the
> > reference clock comes form external crystal oscillator.
>
> Then what does "ref" mean, if gio is the clock supplied externally?

In snps,dw-pcie-common.yaml

	- description:
            Generic reference clock. In case if there are several
            interfaces fed up with a common clock source it's advisable to
            define it with this name (for instance pipe, core and aux can
            be connected to a single source of the periodic signal).
          const: ref

        - description: See native 'ref' clock for details.
          enum: [ gio ]
> We
> talk here about signals coming to this chip, regardless how they are
> generated.

PCIe controller takes one of two reference clocks, internal PLL (controlled
by clock provider) and extern crystal (controller by a GPIO).

There are clk_in and clk_out at SOC. External crystal output connect into
clk_in.

clk_out come from internal pll.

The boards design choose one method (internal pll or use external crystal)

Frank

>
>
> Best regards,
> Krzysztof

RE: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Hongxing Zhu]

> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2025年6月20日 22:41
> To: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
> mode support
> 
> On Fri, Jun 20, 2025 at 03:08:16PM +0200, Krzysztof Kozlowski wrote:
> > On 20/06/2025 10:26, Hongxing Zhu wrote:
> > >> -----Original Message-----
> > >> From: Krzysztof Kozlowski <krzk@kernel.org>
> > >> Sent: 2025年6月20日 15:53
> > >> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > >> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > >> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> > >> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> > >> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > >> kernel@pengutronix.de; festevam@gmail.com;
> > >> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > >> devicetree@vger.kernel.org; imx@lists.linux.dev;
> > >> linux-kernel@vger.kernel.org
> > >> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external
> > >> reference clock mode support
> > >>
> > >> On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
> > >>> On i.MX, the PCIe reference clock might come from either internal
> > >>> system PLL or external clock source.
> > >>> Add the external reference clock source for reference clock.
> > >>>
> > >>> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > >>> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > >>> ---
> > >>>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7
> > >>> ++++++-
> > >>>  1 file changed, 6 insertions(+), 1 deletion(-)
> > >>>
> > >>> diff --git
> > >>> a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> index ca5f2970f217..c472a5daae6e 100644
> > >>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> @@ -219,7 +219,12 @@ allOf:
> > >>>              - const: pcie_bus
> > >>>              - const: pcie_phy
> > >>>              - const: pcie_aux
> > >>> -            - const: ref
> > >>> +            - description: PCIe reference clock.
> > >>> +              oneOf:
> > >>> +                - description: The controller might be configured
> > >> clocking
> > >>> +                    coming in from either an internal system PLL
> > >>> + or
> > >> an
> > >>> +                    external clock source.
> > >>> +                  enum: [ref, gio]
> > >>
> > >> Internal like within PCIe or coming from other SoC block? What does "gio"
> > >> mean?
> > > Internal means that the PCIe reference clock is coming from other
> > > internal SoC block, such as system PLL. "gio" is on behalf that the
> > > reference clock comes form external crystal oscillator.
> >
> > Then what does "ref" mean, if gio is the clock supplied externally?
> 
> In snps,dw-pcie-common.yaml
> 
> 	- description:
>             Generic reference clock. In case if there are several
>             interfaces fed up with a common clock source it's advisable to
>             define it with this name (for instance pipe, core and aux can
>             be connected to a single source of the periodic signal).
>           const: ref
> 
>         - description: See native 'ref' clock for details.
>           enum: [ gio ]
> > We
> > talk here about signals coming to this chip, regardless how they are
> > generated.
> 
> PCIe controller takes one of two reference clocks, internal PLL (controlled by
> clock provider) and extern crystal (controller by a GPIO).
> 
> There are clk_in and clk_out at SOC. External crystal output connect into clk_in.
> 
> clk_out come from internal pll.
> 
> The boards design choose one method (internal pll or use external crystal)
That's right. Thanks.

Best Regards
Richard Zhu
> 
> Frank
> 
> >
> >
> > Best regards,
> > Krzysztof

Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock mode support

[Krzysztof Kozlowski]

On Fri, Jun 20, 2025 at 10:40:52AM -0400, Frank Li wrote:
> On Fri, Jun 20, 2025 at 03:08:16PM +0200, Krzysztof Kozlowski wrote:
> > On 20/06/2025 10:26, Hongxing Zhu wrote:
> > >> -----Original Message-----
> > >> From: Krzysztof Kozlowski <krzk@kernel.org>
> > >> Sent: 2025年6月20日 15:53
> > >> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > >> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > >> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> > >> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> > >> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > >> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> > >> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > >> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > >> Subject: Re: [PATCH v3 1/2] dt-binding: pci-imx6: Add external reference clock
> > >> mode support
> > >>
> > >> On Fri, Jun 20, 2025 at 11:13:49AM GMT, Richard Zhu wrote:
> > >>> On i.MX, the PCIe reference clock might come from either internal
> > >>> system PLL or external clock source.
> > >>> Add the external reference clock source for reference clock.
> > >>>
> > >>> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > >>> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > >>> ---
> > >>>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
> > >>>  1 file changed, 6 insertions(+), 1 deletion(-)
> > >>>
> > >>> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> index ca5f2970f217..c472a5daae6e 100644
> > >>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > >>> @@ -219,7 +219,12 @@ allOf:
> > >>>              - const: pcie_bus
> > >>>              - const: pcie_phy
> > >>>              - const: pcie_aux
> > >>> -            - const: ref
> > >>> +            - description: PCIe reference clock.
> > >>> +              oneOf:
> > >>> +                - description: The controller might be configured
> > >> clocking
> > >>> +                    coming in from either an internal system PLL or
> > >> an
> > >>> +                    external clock source.
> > >>> +                  enum: [ref, gio]
> > >>
> > >> Internal like within PCIe or coming from other SoC block? What does "gio"
> > >> mean?
> > > Internal means that the PCIe reference clock is coming from other
> > >  internal SoC block, such as system PLL. "gio" is on behalf that the
> > > reference clock comes form external crystal oscillator.
> >
> > Then what does "ref" mean, if gio is the clock supplied externally?
> 
> In snps,dw-pcie-common.yaml
> 
> 	- description:
>             Generic reference clock. In case if there are several
>             interfaces fed up with a common clock source it's advisable to
>             define it with this name (for instance pipe, core and aux can
>             be connected to a single source of the periodic signal).
>           const: ref
> 
>         - description: See native 'ref' clock for details.
>           enum: [ gio ]

... ok, but the rest of description is saying: don't use it.

Best regards,
Krzysztof