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From: Oliver Upton To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , nd , "maz@kernel.org" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "will@kernel.org" , "tglx@linutronix.de" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 5/5] KVM: arm64: gic-v5: Probe for GICv5 Message-ID: References: <20250620160741.3513940-1-sascha.bischoff@arm.com> <20250620160741.3513940-6-sascha.bischoff@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250620160741.3513940-6-sascha.bischoff@arm.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250620_132516_431059_060F4573 X-CRM114-Status: GOOD ( 18.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 20, 2025 at 04:07:52PM +0000, Sascha Bischoff wrote: > +/** > + * vgic_v5_probe - probe for a VGICv5 compatible interrupt controller > + * @info: pointer to the GIC description > + * > + * Returns 0 if the VGICv5 has been probed successfully, returns an error code > + * otherwise. > + */ nit: avoid kerneldoc style This actually generates documentation as well as build warnings when we screw up the format. I'd only do this sort of thing for sufficiently public functions. Thanks, Oliver > +int vgic_v5_probe(const struct gic_kvm_info *info) > +{ > + u64 ich_vtr_el2; > + int ret; > + > + if (!info->has_gcie_v3_compat) > + return -ENODEV; > + > + kvm_vgic_global_state.type = VGIC_V5; > + kvm_vgic_global_state.has_gcie_v3_compat = true; > + static_branch_enable(&kvm_vgic_global_state.gicv5_cpuif); > + > + /* We only support v3 compat mode - use vGICv3 limits */ > + kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS; > + > + kvm_vgic_global_state.vcpu_base = 0; > + kvm_vgic_global_state.vctrl_base = NULL; > + kvm_vgic_global_state.can_emulate_gicv2 = false; > + kvm_vgic_global_state.has_gicv4 = false; > + kvm_vgic_global_state.has_gicv4_1 = false; > + > + ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config); > + kvm_vgic_global_state.ich_vtr_el2 = (u32)ich_vtr_el2; > + > + /* > + * The ListRegs field is 5 bits, but there is an architectural > + * maximum of 16 list registers. Just ignore bit 4... > + */ > + kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1; > + > + ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3); > + if (ret) { > + kvm_err("Cannot register GICv3-legacy KVM device.\n"); > + return ret; > + } > + > + static_branch_enable(&kvm_vgic_global_state.gicv3_cpuif); > + kvm_info("GCIE legacy system register CPU interface\n"); > + > + return 0; > +} > + > inline bool kvm_vgic_in_v3_compat_mode(void) > { > if (static_branch_unlikely(&kvm_vgic_global_state.gicv5_cpuif) && > diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h > index 5c78eb915a22..a5292cad60ff 100644 > --- a/arch/arm64/kvm/vgic/vgic.h > +++ b/arch/arm64/kvm/vgic/vgic.h > @@ -308,6 +308,8 @@ int vgic_init(struct kvm *kvm); > void vgic_debug_init(struct kvm *kvm); > void vgic_debug_destroy(struct kvm *kvm); > > +int vgic_v5_probe(const struct gic_kvm_info *info); > + > static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu) > { > struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu; > -- > 2.34.1