From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF51AC7115A for ; Sun, 22 Jun 2025 12:40:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=G39kGGdgOel5ks2KWoZBvfJhe96q0aex/pRGhaP2C9A=; b=uZ1GLrG0RYiwcLkITOaXt0OGdO ZceFJQHtto/Hfxr56KFF7XhCAX2dMRuOT1RhJ66CMj04OlaMmd712f7Ig8zBk6zXeAc/Nxx99rRhq ZYtLCDP42WmBlg46TLzCCji9JcbB6B6s3gzENtlYriHANckXeRTE51kn48OdyzvQDiDPCY7twwMbI DGdaAErxBiFMTSdNo0+DeWjizzAq6h2RFV6UBSBhnsAU4vNphxZIVsfFD641KkzICzWfdCH+FjNsL AqAcHtdEsu6t/PTVowb6sC3bHnB2qNXS2/Nv+RaqHedgyXApLHpcVunEuNq+COw3ZFHZUcZ3YqABc qpNhEZew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uTJzb-00000000rAW-1HCZ; Sun, 22 Jun 2025 12:40:15 +0000 Received: from out-178.mta0.migadu.com ([2001:41d0:1004:224b::b2]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uTJxI-00000000r15-2MHE for linux-arm-kernel@lists.infradead.org; Sun, 22 Jun 2025 12:37:54 +0000 Date: Sun, 22 Jun 2025 05:37:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750595866; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=G39kGGdgOel5ks2KWoZBvfJhe96q0aex/pRGhaP2C9A=; b=hryIEMqT69op4L3cD0N+MNzE3Zcl3j93X5eviPv4N/kD4wosCzZHFO4+k+yidbkKl1X2Ml dRmyMpTYrBM4k1BgLFLAfx+/A/U2efpcJ4JpnChuBkpWs8OpuN7BkD8BSEfx2gMFLk8dCk npfA2UPVzonkTcQe9i5LKkkIrpK1Yzs= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: Sascha Bischoff , "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , nd , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "will@kernel.org" , "tglx@linutronix.de" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 4/5] KVM: arm64: gic-v5: Support GICv3 compat Message-ID: References: <20250620160741.3513940-1-sascha.bischoff@arm.com> <20250620160741.3513940-5-sascha.bischoff@arm.com> <87a560ezpa.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87a560ezpa.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250622_053753_008381_9089FFE9 X-CRM114-Status: GOOD ( 32.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Jun 22, 2025 at 01:19:13PM +0100, Marc Zyngier wrote: > On Fri, 20 Jun 2025 21:20:36 +0100, > Oliver Upton wrote: > > > > Hi Sascha, > > > > Thank you for posting this. Very excited to see the GICv5 enablement get > > started. > > > > On Fri, Jun 20, 2025 at 04:07:51PM +0000, Sascha Bischoff wrote: > > > Add support for GICv3 compat mode (FEAT_GCIE_LEGACY) which allows a > > > GICv5 host to run GICv3-based VMs. This change enables the > > > VHE/nVHE/hVHE/protected modes, but does not support nested > > > virtualization. > > > > Can't we just load the shadow state into the compat VGICv3? I'm worried > > this has sharp edges on the UAPI side as well as users wanting to > > migrate VMs to new hardware. > > > > The guest hypervisor should only see GICv3-only or GICv5-only, we can > > pretend FEAT_GCIE_LEGACY never existed :) > > That's exactly what this does. And the only reason NV isn't supported > yet is the current BET0 spec makes ICC_SRE_EL2 UNDEF at EL1 with NV, > which breaks NV in a spectacular way. Gee, I wonder how... :) > This will be addressed in a future revision of the architecture, and > no HW will actually be built with this defect. As such, there is no > UAPI to break. That's fine by me. TBH, when I left this comment I hadn't fully read the patch yet and was more curious about the intent. > > > +void __vgic_v3_compat_mode_disable(void) > > > +{ > > > + sysreg_clear_set_s(SYS_ICH_VCTLR_EL2, ICH_VCTLR_EL2_V3, 0); > > > + isb(); > > > +} > > > + > > > > It isn't clear to me what these ISBs are synchonizing against. AFAICT, > > the whole compat thing is always visible and we can restore the rest of > > the VGICv3 context before guaranteeing the enable bit has been observed. > > No, some registers have a behaviour that is dependent on the status of > the V3 bit (ICH_VMCR_EL2 being one), so that synchronisation is > absolutely needed before accessing this register. Yeah, I had followed up on this after reading the spec, modal registers are great. Putting all the constituent registers together in the common load/put helpers will clear that up. > The disabling is probably the wrong way around though, and I'd expect > the clearing of V3 to have an ISB *before* the write to the sysreg, > > > Can we consolidate this into a single hyp call along with > > __vgic_v3_*_vmcr_aprs()? > > I agree that we should be able to move this to be driven by > load/put entirely. > > But we first need to fix the whole WFI sequencing first, because this > is a bit of a train wreck at the moment (entering the WFI emulation > results in *two* "put" sequences on the vgic, and exiting WFI results > in two loads). You're talking about the case where halt polling fails and we do a put/load on the whole vCPU to schedule right? i.e. in addition to the explicit put on the vgic for faithful emulation. Thanks, Oliver