* [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
2025-06-13 12:48 [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
@ 2025-06-13 12:48 ` Niklas Cassel
2025-06-23 14:25 ` Manivannan Sadhasivam
2025-06-13 12:48 ` [PATCH v3 3/6] PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ Niklas Cassel
2025-06-23 10:12 ` [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2 siblings, 1 reply; 5+ messages in thread
From: Niklas Cassel @ 2025-06-13 12:48 UTC (permalink / raw)
To: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner
Cc: Wilfred Mallawa, Damien Le Moal, Laszlo Fiat, Niklas Cassel,
linux-pci, linux-rockchip, linux-arm-kernel
Macro PCIE_RESET_CONFIG_WAIT_MS was added to pci.h in commit d5ceb9496c56
("PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value").
Later, in commit 70a7bfb1e515 ("PCI: rockchip-host: Wait 100ms after reset
before starting configuration"), PCIE_T_RRS_READY_MS was added to pci.h.
These macros are duplicates, and represent the exact same delay in the
PCIe specification.
Since the comment above PCIE_RESET_CONFIG_WAIT_MS is strictly more correct
than the comment above PCIE_T_RRS_READY_MS, change rockchip-host to use
PCIE_RESET_CONFIG_WAIT_MS, and remove PCIE_T_RRS_READY_MS, as
rockchip-host is the only user of this macro.
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
drivers/pci/controller/pcie-rockchip-host.c | 2 +-
drivers/pci/pci.h | 7 -------
2 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index b9e7a8710cf0..c11ed45c25f6 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -325,7 +325,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
msleep(PCIE_T_PVPERL_MS);
gpiod_set_value_cansleep(rockchip->perst_gpio, 1);
- msleep(PCIE_T_RRS_READY_MS);
+ msleep(PCIE_RESET_CONFIG_WAIT_MS);
/* 500ms timeout value should be enough for Gen1/2 training */
err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 98d6fccb383e..819833e57590 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -35,13 +35,6 @@ struct pcie_tlp_log;
*/
#define PCIE_T_PERST_CLK_US 100
-/*
- * End of conventional reset (PERST# de-asserted) to first configuration
- * request (device able to respond with a "Request Retry Status" completion),
- * from PCIe r6.0, sec 6.6.1.
- */
-#define PCIE_T_RRS_READY_MS 100
-
/*
* PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
* Recommends 1ms to 10ms timeout to check L2 ready.
--
2.49.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
2025-06-13 12:48 ` [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
@ 2025-06-23 14:25 ` Manivannan Sadhasivam
0 siblings, 0 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2025-06-23 14:25 UTC (permalink / raw)
To: Niklas Cassel
Cc: Shawn Lin, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, Bjorn Helgaas, Heiko Stuebner, Wilfred Mallawa,
Damien Le Moal, Laszlo Fiat, linux-pci, linux-rockchip,
linux-arm-kernel
On Fri, Jun 13, 2025 at 02:48:41PM +0200, Niklas Cassel wrote:
> Macro PCIE_RESET_CONFIG_WAIT_MS was added to pci.h in commit d5ceb9496c56
s/PCIE_RESET_CONFIG_WAIT_MS/PCIE_RESET_CONFIG_DEVICE_WAIT_MS
> ("PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value").
>
> Later, in commit 70a7bfb1e515 ("PCI: rockchip-host: Wait 100ms after reset
> before starting configuration"), PCIE_T_RRS_READY_MS was added to pci.h.
>
> These macros are duplicates, and represent the exact same delay in the
> PCIe specification.
>
> Since the comment above PCIE_RESET_CONFIG_WAIT_MS is strictly more correct
> than the comment above PCIE_T_RRS_READY_MS, change rockchip-host to use
> PCIE_RESET_CONFIG_WAIT_MS, and remove PCIE_T_RRS_READY_MS, as
> rockchip-host is the only user of this macro.
>
> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
LGTM!
- Mani
> ---
> drivers/pci/controller/pcie-rockchip-host.c | 2 +-
> drivers/pci/pci.h | 7 -------
> 2 files changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index b9e7a8710cf0..c11ed45c25f6 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -325,7 +325,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
> msleep(PCIE_T_PVPERL_MS);
> gpiod_set_value_cansleep(rockchip->perst_gpio, 1);
>
> - msleep(PCIE_T_RRS_READY_MS);
> + msleep(PCIE_RESET_CONFIG_WAIT_MS);
>
> /* 500ms timeout value should be enough for Gen1/2 training */
> err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 98d6fccb383e..819833e57590 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -35,13 +35,6 @@ struct pcie_tlp_log;
> */
> #define PCIE_T_PERST_CLK_US 100
>
> -/*
> - * End of conventional reset (PERST# de-asserted) to first configuration
> - * request (device able to respond with a "Request Retry Status" completion),
> - * from PCIe r6.0, sec 6.6.1.
> - */
> -#define PCIE_T_RRS_READY_MS 100
> -
> /*
> * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
> * Recommends 1ms to 10ms timeout to check L2 ready.
> --
> 2.49.0
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 3/6] PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
2025-06-13 12:48 [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
@ 2025-06-13 12:48 ` Niklas Cassel
2025-06-23 10:12 ` [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2 siblings, 0 replies; 5+ messages in thread
From: Niklas Cassel @ 2025-06-13 12:48 UTC (permalink / raw)
To: Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Kever Yang, Shawn Lin
Cc: Wilfred Mallawa, Damien Le Moal, Laszlo Fiat, Niklas Cassel,
Simon Xue, linux-pci, linux-arm-kernel, linux-rockchip
Per PCIe r6.0, sec 6.6.1, software must generally wait a minimum of
100ms (PCIE_RESET_CONFIG_WAIT_MS) after Link training completes before
sending a Configuration Request.
Prior to ec9fd499b9c6 ("PCI: dw-rockchip: Don't wait for link since
we can detect Link Up"), dw-rockchip used dw_pcie_wait_for_link(),
which waited between 0 and 90ms after the link came up before we
enumerate the bus, and this was apparently enough for most devices.
After ec9fd499b9c6, rockchip_pcie_rc_sys_irq_thread() started
enumeration immediately when handling the link-up IRQ, and devices
(e.g., Laszlo Fiat's PLEXTOR PX-256M8PeGN NVMe SSD) may not be ready
to handle config requests yet.
Delay PCIE_RESET_CONFIG_WAIT_MS after the link-up IRQ before starting
enumeration.
Cc: Laszlo Fiat <laszlo.fiat@proton.me>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 93171a392879..108d30637920 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -458,6 +458,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
if (reg & PCIE_RDLH_LINK_UP_CHGED) {
if (rockchip_pcie_link_up(pci)) {
+ msleep(PCIE_RESET_CONFIG_WAIT_MS);
dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
/* Rescan the bus to enumerate endpoint devices */
pci_lock_rescan_remove();
--
2.49.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready
2025-06-13 12:48 [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 3/6] PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ Niklas Cassel
@ 2025-06-23 10:12 ` Niklas Cassel
2 siblings, 0 replies; 5+ messages in thread
From: Niklas Cassel @ 2025-06-23 10:12 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Heiko Stuebner, Shawn Lin, Kevin Xie, Kever Yang
Cc: Wilfred Mallawa, Damien Le Moal, Laszlo Fiat, Simon Xue,
linux-pci, linux-arm-kernel, linux-rockchip, linux-arm-msm
On Fri, Jun 13, 2025 at 02:48:39PM +0200, Niklas Cassel wrote:
> Hello all,
>
> The DWC PCIe controller driver currently does not follow the PCIe
> specification with regards to the delays after link training, before
> sending out configuration requests. This series fixes this.
>
> At the same time, PATCH 1/4 addresses a regression where a Plextor
> NVMe drive fails to be configured correctly. With this series, the
> Plextor NVMe drive works once again.
>
>
> Kind regards,
> Niklas
>
>
> Changes since v2:
> -Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS.
>
>
> Niklas Cassel (6):
> PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to
> PCIE_RESET_CONFIG_WAIT_MS
> PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
> PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
> PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
> PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link
> up
> PCI: dwc: Reduce LINK_WAIT_SLEEP_MS
>
> drivers/pci/controller/dwc/pcie-designware.c | 13 ++++++++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 13 +++++++++----
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
> drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> drivers/pci/controller/pcie-rockchip-host.c | 2 +-
> drivers/pci/controller/plda/pcie-starfive.c | 2 +-
> drivers/pci/pci.h | 9 +--------
> 7 files changed, 26 insertions(+), 15 deletions(-)
>
> --
> 2.49.0
>
Gentle ping
^ permalink raw reply [flat|nested] 5+ messages in thread