From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
"maz@kernel.org" <maz@kernel.org>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"will@kernel.org" <will@kernel.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
Timothy Hayes <Timothy.Hayes@arm.com>
Subject: Re: [PATCH 1/5] irqchip/gic-v5: Skip deactivate for forwarded PPI interrupts
Date: Mon, 23 Jun 2025 17:21:06 +0200 [thread overview]
Message-ID: <aFlw4lOj8tUGrSTb@lpieralisi> (raw)
In-Reply-To: <20250620160741.3513940-2-sascha.bischoff@arm.com>
On Fri, Jun 20, 2025 at 04:07:50PM +0000, Sascha Bischoff wrote:
> If a PPI interrupt is forwarded to a guest, skip the deactivate and
> only EOI. Rely on the guest deactivating the both the virtual and
"deactivating both"
> physical interrupts (due to ICH_LRx_EL2.HW being set) later on as part
> of handling the injected interrupt. This mimics the behaviour seen on
> native GICv3.
>
> This is part of adding support for the GICv3 compatibility mode on a
> GICv5 host.
>
> Co-authored-by: Timothy Hayes <timothy.hayes@arm.com>
> Signed-off-by: Timothy Hayes <timothy.hayes@arm.com>
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> ---
> drivers/irqchip/irq-gic-v5.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
Reviewed-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
> diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c
> index 4a0990f46358..28853d51a2ea 100644
> --- a/drivers/irqchip/irq-gic-v5.c
> +++ b/drivers/irqchip/irq-gic-v5.c
> @@ -213,6 +213,12 @@ static void gicv5_hwirq_eoi(u32 hwirq_id, u8 hwirq_type)
>
> static void gicv5_ppi_irq_eoi(struct irq_data *d)
> {
> + /* Skip deactivate for forwarded PPI interrupts */
> + if (irqd_is_forwarded_to_vcpu(d)) {
> + gic_insn(0, CDEOI);
> + return;
> + }
> +
> gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_PPI);
> }
>
> @@ -494,6 +500,16 @@ static bool gicv5_ppi_irq_is_level(irq_hw_number_t hwirq)
> return !!(read_ppi_sysreg_s(hwirq, PPI_HM) & bit);
> }
>
> +static int gicv5_ppi_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
> +{
> + if (vcpu)
> + irqd_set_forwarded_to_vcpu(d);
> + else
> + irqd_clr_forwarded_to_vcpu(d);
> +
> + return 0;
> +}
> +
> static const struct irq_chip gicv5_ppi_irq_chip = {
> .name = "GICv5-PPI",
> .irq_mask = gicv5_ppi_irq_mask,
> @@ -501,6 +517,7 @@ static const struct irq_chip gicv5_ppi_irq_chip = {
> .irq_eoi = gicv5_ppi_irq_eoi,
> .irq_get_irqchip_state = gicv5_ppi_irq_get_irqchip_state,
> .irq_set_irqchip_state = gicv5_ppi_irq_set_irqchip_state,
> + .irq_set_vcpu_affinity = gicv5_ppi_irq_set_vcpu_affinity,
> .flags = IRQCHIP_SKIP_SET_WAKE |
> IRQCHIP_MASK_ON_SUSPEND,
> };
> --
> 2.34.1
next prev parent reply other threads:[~2025-06-23 18:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-20 16:07 [PATCH 0/5] KVM: arm64: Enable GICv3 guests on GICv5 hosts using FEAT_GCIE_LEGACY Sascha Bischoff
2025-06-20 16:07 ` [PATCH 1/5] irqchip/gic-v5: Skip deactivate for forwarded PPI interrupts Sascha Bischoff
2025-06-23 15:21 ` Lorenzo Pieralisi [this message]
2025-06-27 9:49 ` Sascha Bischoff
2025-06-20 16:07 ` [PATCH 3/5] arm64/sysreg: Add ICH_VCTLR_EL2 Sascha Bischoff
2025-06-20 16:07 ` [PATCH 4/5] KVM: arm64: gic-v5: Support GICv3 compat Sascha Bischoff
2025-06-20 20:20 ` Oliver Upton
2025-06-20 23:02 ` Oliver Upton
2025-06-23 13:11 ` Sascha Bischoff
2025-06-22 12:19 ` Marc Zyngier
2025-06-22 12:37 ` Oliver Upton
2025-06-23 13:02 ` Sascha Bischoff
2025-06-20 16:07 ` [PATCH 2/5] irqchip/gic-v5: Populate struct gic_kvm_info Sascha Bischoff
2025-06-23 15:14 ` Lorenzo Pieralisi
2025-06-27 9:49 ` Sascha Bischoff
2025-06-20 16:07 ` [PATCH 5/5] KVM: arm64: gic-v5: Probe for GICv5 Sascha Bischoff
2025-06-20 20:25 ` Oliver Upton
2025-06-23 13:12 ` Sascha Bischoff
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